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A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically connected to the south bridge. The

A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically connected to the south bridge. The south bridge includes a register for storings a plurality of pre-fetched read data to provide the pre-fetched read data to the peripheral device. The north bridge has an address queue module for storing an address of the pre-fetched read data, and a snooping module for checking whether a data value corresponding to the address is updated by the CPU. The north bridge assists the south bridge in obtaining and maintaining the pre-fetched read data for high efficiency and accuracy of read caching of the south bridge.

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1. A chip set electrically connected to a central processing unit (CPU) and a peripheral device, comprising: a south bridge electrically connected to the peripheral device, the south bridge having a register for storing a plurality of pre-fetched data to provide the pre-fetched data to the periphera

1. A chip set electrically connected to a central processing unit (CPU) and a peripheral device, comprising: a south bridge electrically connected to the peripheral device, the south bridge having a register for storing a plurality of pre-fetched data to provide the pre-fetched data to the peripheral device while being requested, wherein an adjoining data of a peripheral data is fetched as the pre-fetched data, and the peripheral data is requested by the peripheral device, and the addresses of the pre-fetched data and the addresses of the peripheral data are sequential; anda north bridge electrically connected to the CPU and the south bridge, the north bridge comprising: an address queue module for storing addresses of the pre-fetched data; anda snooping module for snooping a cache in the CPU according to the addresses of the pre-fetched data in the address queue to determine whether the pre-fetched data is updated and to ensure data coherence between the register and the cache. 2. The chip set of claim 1, wherein the pre-fetched data in the register is deleted while the pre-fetched data is updated by the CPU. 3. The chip set of claim 2, wherein while the pre-fetched data is updated, the north bridge transfers the updated pre-fetched data to the register. 4. The chip set of claim 1, wherein the snooping module periodically snoops the cache in the CPU according to the addresses in the address queue for checking whether the pre-fetched data in the register is updated by the CPU. 5. The chip set of claim 1, wherein the snooping module snoops the cache in the CPU according to the addresses in the address queue while writing data from the cache to a memory via the north bridge. 6. A computer system comprising: a central processing unit (CPU) comprising a cache for caching data;a memory for storing data where each data has a corresponding address;a peripheral device;a south bridge electrically connected to the peripheral device, the south bridge having a register for storing a plurality of pre-fetched read data to provide the pre-fetched read data to the peripheral device while being requested, wherein an adjoining data of a peripheral data is fetched as the pre-fetched data, and the peripheral data is requested by the peripheral device, and the addresses of the pre-fetched data and the addresses of the peripheral data are sequential; anda north bridge electrically connected to the CPU and the memory, the north bridge comprising: an address queue module for storing addresses of the pre-fetched data; anda snooping module for snooping a cache in the CPU according to the addresses of the pre-fetched data in the address queue to determine whether the pre-fetched data is updated and to ensure data coherence between the register and the cache. 7. The computer system of claim 6, wherein the pre-fetched data in the register is deleted by the south bridge when the pre-fetched data is updated by the CPU. 8. The computer system of claim 7, while the pre-fetched data is updated, the north bridge transfers the updated pre-fetched data to the register. 9. The computer system of claim 6, wherein the snooping module periodically snoops the cache according to the addresses in the address queue for checking whether the pre-fetched data in the register is updated by the CPU. 10. The computer system of claim 6, wherein the snooping module snoops the cache according to the addresses in the address queue while writing data from the cache to a memory via the north bridge. 11. The computer system of claim 6 wherein the peripheral data are obtained from the memory. 12. A method for cohering a plurality of pre-fetched data, the method comprising: storing pre-fetched data in a south bridge while transmitting peripheral data to a peripheral device, the addresses of the pre-fetched data and the addresses of the peripheral data being sequential;storing addresses of the pre-fetched data in a north bridge; andsnooping a cache in a CPU to determine whether the pre-fetched data is updated and to ensure data coherence between the south bridge and the cache. 13. The method of claim 12 further comprising: deleting the pre-fetched data in the south bridge while the pre-fetched data is updated. 14. The method of claim 13 further comprising: transmitting the updated pre-fetched data to the south bridge. 15. The method of claim 12 comprising snooping the cache according to the addresses of the pre-fetched data in the north bridge.