Methods and apparatus for compiling instructions for a data processor
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/44
G06F-009/45
출원번호
US-0906519
(2007-10-01)
등록번호
US-8166450
(2012-04-24)
발명자
/ 주소
Fuhler, Richard A.
Pennello, Thomas J.
Jalkut, Michael Lee
Warnes, Peter
출원인 / 주소
Synopsys, Inc.
대리인 / 주소
Fenwick & West LLP
인용정보
피인용 횟수 :
20인용 특허 :
82
초록▼
Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approach
Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.
대표청구항▼
1. A method of register allocation for use by a pipelined digital processor having a mixed-length instruction set architecture, the method executed by the processor and comprising: storing data in a register from a first set of registers, the first set of registers associated with a first instructio
1. A method of register allocation for use by a pipelined digital processor having a mixed-length instruction set architecture, the method executed by the processor and comprising: storing data in a register from a first set of registers, the first set of registers associated with a first instruction set of a first length;evaluating, using graph theory, whether spilling of the register from the first set of registers to a second set of registers is required, the second set of registers associated with a second instruction set of a second length; andresponsive to evaluating that spilling is required, reassigning the data in the register from the first set of registers to a register from the second set of registers. 2. The method of claim 1, wherein the first instruction set of the first length comprises instructions of a 16-bit length and the second instruction set of the second length comprises instructions of a 32-bit length. 3. The method of claim 1, further comprising: responsive to evaluating that spilling is required, coalescing instructions associated with one or more registers from the first set of registers and the second set of registers to reduce a number of instructions. 4. The method of claim 3, wherein coalescing instructions comprises: determining a first version of a plurality of instructions associated with the first set of registers and the second set of registers, the first version determined according to the first instruction set of the first length;determining a second version of the plurality of instructions associated with the first set of registers and the second set of registers, the second version determined according to the second instruction set of the second length;determining for a portion of the plurality of instructions whether the first version or the second version is better in terms of size of instruction or number of instructions; andselecting the better version of the portion of the plurality of instructions. 5. The method of claim 4, wherein determining whether the first version or the second version is better is based on size of the portion of the plurality of instructions in the first version and second version. 6. The method of claim 4, wherein determining whether the first version or the second version is better is based on a number of instructions in the first version and second version of the portion of the plurality of instructions. 7. The method of claim 1, further comprising: assigning a different characteristic to the register that is going to be spilled; andperforming a common sub-expression elimination process. 8. The method of claim 1, further comprising: assigning a priority to each register from the first set of registers. 9. The method of claim 1, further comprising: assigning a specific characteristic for at least one register from the first set of registers based at least in part on at least one of: (i) compressing a size of an instruction of the at least one register, or (ii) reducing an overall size of a compiled function. 10. The method of claim 1, further comprising: assigning characteristics to each register from the first set of registers and the second set of registers; andassigning a different characteristic to the register from the first set of registers that is going to be spilled. 11. A digital processor having a mixed-length instruction set architecture, the processor comprising: a first set of registers associated with a first instruction set of a first length; anda second set of registers associated with a second instruction set of a second length;wherein data stored in a register from the first set of registers is reassigned to a register from the second set of registers responsive to evaluating that spilling is required. 12. The digital processor of claim 11, wherein the first instruction set of the first length comprises instructions of a 16-bit length and the second instruction set of the second length comprises instructions of a 32-bit length. 13. The digital processor of claim 11, wherein instructions associated with one or more registers from the first set of registers and the second set of registers is coalesced to reduce a number of instructions responsive to spilling. 14. The digital processor of claim 13, wherein the digital processor is configured to reduce the number of instructions by: determining a first version of a plurality of instructions associated with the first set of registers and the second set of registers, the first version determined according to the first instruction set of the first length;determining a second version of the plurality of instructions associated with the first set of registers and the second set of registers, the second version determined according to the second instruction set of the second length;determining for a portion of the plurality of instructions whether the first version or the second version is better in terms of size of instruction or number of instructions; andselecting the better version of the portion of the plurality of instructions. 15. The digital processor of claim 14, wherein determining whether the first version or the second version is better is based on size of the portion of the plurality of instructions in the first version and second version. 16. The digital processor of claim 14, wherein determining whether the first version or the second version is better is based on a number of instructions in the first version and second version of the portion of the plurality of instructions. 17. The digital processor of claim 11, wherein the digital processor is configured to: assign a different characteristic to the register that is going to be spilled; andperform a common sub-expression elimination process. 18. The digital processor of claim 11, wherein each register from the first set of registers is assigned a priority. 19. The digital processor of claim 11, wherein the digital processor is configured to: assign characteristics to each register from the first set of registers and the second set of registers; andassign a different characteristic to the register from the first set of registers that is going to be spilled. 20. The digital processor of claim 11, wherein evaluating that spilling is required comprising using graph coloring for the evaluation.
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Songer, Christopher Mark; Konas, Pavlos; Gauthier, Marc E.; Chea, Kevin C., Abstraction of configurable processor functionality for operating systems portability.
Rau Bantwai R. (Los Altos CA) Schlansker Michael (Sunnyvale CA), Analysis and optimization of array variables in compiler for instruction level parallel processor.
Douniwa Kenichi,JPX, Apparatus and method for compiling a plurality of instruction sets for a processor and a media for recording the compiling method.
Kametani Masatsugu (Ibaraki JPX), Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus.
Earl A. Killian ; Ricardo E. Gonzalez ; Ashish B. Dixit ; Monica Lam ; Walter D. Lichtenstein ; Christopher Rowen ; John C. Ruttenberg ; Robert P. Wilson ; Albert Ren-Rui Wang ; Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
Killian, Earl A.; Gonzalez, Ricardo E.; Dixit, Ashish B.; Lam, Monica; Lichtenstein, Walter D.; Rowen, Christopher; Ruttenberg, John C.; Wilson, Robert P.; Wang, Albert Ren-Rui; Maydan, D{grave over , Automated processor generation system for designing a configurable processor and method for the same.
Sato Taizo (Kawasaki JPX) Fujihira Atsushi (Kawasaki JPX), Cache memory and data processor including instruction length decoding circuitry for simultaneously decoding a plurality.
Vincent Phuoc Cao ; Lincoln A. Fajardo ; Sanjay Jinturkar ; Gang-Ryung Uh ; Yuhong Wang ; David B. Whalley, Compiler optimization techniques for exploiting a zero overhead loop mechanism.
Utsumi Isao (Tokyo JPX) Mori Yoshikazu (Tokyo JPX), Compiler system using reordering of microoperations to eliminate interlocked instructions for pipelined processing of as.
Batten Dean ; D'Arcy Paul Gerard ; Glossner C. John ; Jinturkar Sanjay ; Thilo Jesse ; Vassiliadis Stamatis,NLX ; Wires Kent E., Compiler-controlled dynamic instruction dispatch in pipelined processors.
Miyamoto Takashi,JPX, Compiling method for generating target program in accordance with target processor type, compiling device, recording medium with compiling program recorded therein and recording medium with conversio.
Charles Philippe G. (Brooklyn NY) Fisher ; Jr. Gerald A. (Croton-on-Hudson NY), Compressed LR parsing table and method of compressing LR parsing tables.
Hampapuram Hari ; Lee Yen C ; Jacobs Eino ; Ang Michael, Compressed instruction format for use in a VLIW processor and processor for processing such instructions.
Lee Ruby B. (Cupertino CA) Mahon Michael J. (San Jose CA), Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward s.
Toi,Takao; Awashima,Toru; Miyazawa,Yoshiyuki; Nakamura,Noritsugu; Fujii,Taro; Furuta,Koichiro; Motomura,Masato, Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus.
Cofler, Andrew; Bouvier, Stephane; Wojcieszak, Laurent, Decoding next instruction of different length without length mode indicator change upon length change instruction detection.
Briggs Preston P. (Houston TX) Cooper Keith D. (Houston TX) Kennedy ; Jr. Kenneth W. (Houston TX) Torczon Linda M. (Houston TX), Digital computer register allocation and code spilling using interference graph coloring.
Spielman Jason ; Huang Yee-Wei ; Gallup ; deceased Michael G. ; Seaton ; Jr. Robert W. ; Goke L. Rodney, Efficient stack utilization for compiling and executing nested if-else constructs in a vector data processing system.
Killian Earl A. ; Gonzalez Ricardo E. ; Dixit Ashish B. ; Lam Monica ; Lichtenstein Walter D. ; Rowen Christopher ; Ruttenberg John C. ; Wilson Robert P., High data density RISC processor.
Miller Richard G. ; Cardillo Louis A. ; Mathieson John G. ; Smith Eric R., Instruction compression and decompression system and method for a processor.
Worrell Frank ; Ekner Hartvig,DKX, Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a micropro.
Odnert Daryl (Boulder Creek CA) Santhanam Vatsa (Sunnyvale CA), Method and apparatus for compiling computer programs with interprocedural register allocation.
Odnert Daryl (Boulder Creek CA) Santhanam Vatsa (Sunnyvale CA), Method and apparatus for compiling computer programs with interproceduural register allocation.
Hakewill, James Robert Howard; Khan, Mohammed Noshad; Plowman, Edward, Method and apparatus for managing the configuration and functionality of a semiconductor design.
Raje Prasad A. ; Siu Stuart C., Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker with.
Faraboschi Paolo ; Fisher Joseph A., Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition.
Lee Sherman ; Halligan JoAnne K., Method for compiling a software program and executing on a system which converts data between different endian formats.
Nishiyama Hiroyasu,JPX ; Kikuchi Sumio,JPX ; Mori Noriyasu,JPX ; Nishimoto Akira,JPX ; Takeuchi Yooichi,JPX, Method for controlling a processor for power-saving in a computer for executing a program, compiler medium and processo.
David Francis Bacon ; Johannes C. Laffra ; Peter Francis Sweeney ; Frank Tip, Method for determining reachable methods in object-oriented applications that use class libraries.
Hall Charles B. (Toronto TX CAX) Markstein Peter W. (Austin TX) O\Brien J. Kevin (Scarborough CAX), Method for improving the efficiency of arithmetic code generation in an optimizing compiler using machine independent up.
Coon Brett (San Jose CA) Miyayama Yoshiyuki (Santa Clara CA) Nguyen Le T. (Monte Sereno CA) Wang Johannes (Redwood City CA), Method for translating non-native instructions to native instructions and combining them into a final bucket for process.
Gerald G. Pechanek ; Charles W. Kurak, Jr. ; Larry D. Larsen, Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture.
Smith Stewart G. (Valbonne FRX) Morgan Ralph W. (La Colle sur Loup FRX) Payne Julian G. (Antibes FRX), Methods of realizing digital signal processors using a programmed compiler.
Shiell Jonathan H. ; Steiss Donald E., Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instr.
Battle James Thomas ; Hung Andy C. ; Purcell Stephen C., Multimedia processor using variable length instructions with opcode specification of source operand as result of prior i.
Hammond Gary N. (Campbell CA) Kahn Kevin C. (Portland OR) Alpert Donald B. (Santa Clara CA), Processor capable of executing programs that contain RISC and CISC instructions.
Otani Sugako,JPX ; Iwata Shunichi,JPX, Processor for executing instruction codes of two different lengths and device for inputting the instruction codes.
Aizikowitz Nava Arela,ILX ; Asnash Liviu,ILX ; Bar-Haim Roy,ILX ; Prosser Edward Curtis ; Roediger Robert Ralph ; Schmidt William Jon, Register allocation method and apparatus for gernerating spill code as a function of register pressure compared to dual.
Vasilevsky Alexander D. (Watertown MA) Sabot Gary W. (Cambridge MA) Lasser Clifford A. (Cambridge MA) Tennies Lisa A. (Bedford MA) Weinberg Tobias M. (Somerville MA) Seamonson Linda J. (Wellesley MA), System and method for compiling a fine-grained array based source program onto a course-grained hardware.
Harris Kevin W. (Nashua NH) Noyce William B. (Hollis NH), System and method for controlling execution of nested loops in parallel in a computer including multiple processors, and.
Wilson, Robert P.; Maydan, Dror E.; Wang, Albert Ren-Rui; Lichtenstein, Walter D.; Tjiang, Weng Kiang, System and method for dynamically designing and evaluating configurable processor instructions.
Eickemeyer Richard J. (Binghamton NY) Vassiliadis Stamatis (Vestal NY), System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution.
Blomgren James S. ; Brashears Cheryl Senter, Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture.
Gschwind, Michael Karl; Montoye, Robert Kevin; Olsson, Brett; Wellman, John-David, Methods for generating code for an architecture encoding an extended register specification.
Srinivasan, Nagaraj; Anbuselvan, Ananthalakshmi; Rangarajan, Keshava; Krishnamurthy, Sudharsan; Sinha, Murari; Chen, Yuling; Rao, Aditya Ramamurthy; Dasararaju, Jayateja; Gupta, Harish, System and method for meta-data driven, semi-automated generation of web services based on existing applications.
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Susnea, Adriana Maria; Grover, Vinod; Lee, Sean Youngsung, System, method, and computer program product for optimizing the management of thread stack memory.
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