초록 ▼

Integrated circuit (1) comprising: an array of single photon avalanche diodes (SPADs),a plurality of read-out circuits, each SPADs being coupled to one read-out circuit, wherein at least some of the read-out circuits comprise time-to-digital converters (TDC) and/or a digital asynchronous counter,whe

Integrated circuit (1) comprising: an array of single photon avalanche diodes (SPADs),a plurality of read-out circuits, each SPADs being coupled to one read-out circuit, wherein at least some of the read-out circuits comprise time-to-digital converters (TDC) and/or a digital asynchronous counter,wherein a plurality of SPADs are coupled to one single read-out circuit. The read-out circuit may comprise a transformer for decoupling the SPAD from other parts of said read-out circuit.

대표청구항 ▼

1. An integrated circuit comprising an array of integrated single photon avalanche photodiode (SPAD) having an avalanche junction comprising an integrated transformer to avoid premature breakdown of the avalanche junction and/or to quench the photodiode. 2. The integrated circuit of claim 1, said tr

1. An integrated circuit comprising an array of integrated single photon avalanche photodiode (SPAD) having an avalanche junction comprising an integrated transformer to avoid premature breakdown of the avalanche junction and/or to quench the photodiode. 2. The integrated circuit of claim 1, said transformer being implemented by using resistive layers. 3. The integrated circuit of claim 1, said transformer decoupling said SPAD from other parts of said circuit. 4. The integrated circuit of claim 1, said transformer comprising a first coil and a second coil, said first coil being arranged so that avalanche current triggered by photons through said SPAD flows through said first coil, thus generating an electrical pulse in said second coil. 5. The integrated circuit of claim 3, further comprising a circuit for converting said pulse through said second coil into a digital, CMOS compatible pulse. 6. The integrated circuit of claim 1, comprising a substrate being part of the PN junction where the avalanche is triggered by photons, a bias voltage being applied through said transformer on the other side of said junction. 7. The integrated circuit of claim 1, said transformer being fabricated using one of the following: superimposed polysilicon layers, lateral polysilicon layers, superimposed metal layers, lateral metal layers, superimposed polysilicon and metal layers, and/or lateral polysilicon and metal layers. 8. A CMOS circuit comprising at least one CMOS implemented single photon avalanche photodiode (SPAD) having an avalanche junction and a corresponding number of associated integrated transformers, at least one associated integrated transformers connected in series with each of said SPADs to avoid premature breakdown of the avalanche junction or to quench the photodiode. 9. An integrated circuit comprising: an array of single photon avalanche diodes (SPADs), each SPAD comprising or being associated with an integrated transformer, the number of integrated transformers corresponding to the number of SPADs in the array, each SPAD being connected in series with one coil of the corresponding transformer. 10. An imager circuit comprising an array of integrated photodiodes, the photodiodes being arranged in groups, each group comprising at least one photodiode, a plurality of integrated transformers, the number of transformers corresponding to the number of groups of photodiodes, each group being associated with an integrated transformer decoupling said photodiode from other parts of said imager circuit. 11. A method for galvanically decoupling at least one avalanche diode in an integrated array of avalanche diode, said method comprising a step of connecting said avalanche diode with a first integrated coil and connecting another component with a second integrated coil, said first and second integrated coils forming a transformer.