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Conductive routings in integrated circuits using under bump metallization

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-029/76
출원번호 US-0343261 (2008-12-23)
등록번호 US-8169081 (2012-05-01)
발명자 / 주소
  • Jergovic, Ilija
  • Lacap, Efren M.
출원인 / 주소
  • Volterra Semiconductor Corporation
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 12  인용 특허 : 158

초록

An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump meta

대표청구항

1. An integrated circuit structure comprising: a first conductive layer below an uppermost passivation layer, the first conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region;an under bump metallization layer over the f

이 특허에 인용된 특허 (158)

  1. Fujisawa Yukio (Hyogo JPX) Takinoue Isao (Hyogo JPX), All digital switching regulator for use in power supplies, battery chargers, and DC motor control circuits.
  2. Burns Carmen D. (San Jose CA), Antioxidant coating of copper parts for thermal compression gang bonding of semiconductive devices.
  3. Salman Akram ; Alan G. Wood ; Warren M. Farnworth, Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer.
  4. Duley Raymond S. (Buda TX), Apparatus for modifying an electrical signal.
  5. Pohlman,William; Eisele,Michael, Apparatus for providing regulated power to an integrated circuit.
  6. William Pohlman ; Michael Eisele, Apparatus for providing regulated power to an integrated circuit.
  7. Padmanabhan Gobi R., Array of solder pads on an integrated circuit.
  8. Boros Victor B. (New York NY) Giacopelli James N. (Maspeth NY) Papathomas Thomas V. (Chatham NJ), Average current controlled switching regulator utilizing digital control techniques.
  9. Tamio Humphrey ; Salvador Salcido, Jr., Ball grid array package with supplemental electronic component.
  10. Dhong Sang H. (Mahopac NY) Shin Hyun J. (Mahopac NY) Hwang Wei (Armonk NY), Bandgap voltage reference generator.
  11. Davis ; Jr. James B. (Merrimack NH), Battery charger for charging a plurality of batteries.
  12. Hallberg Alan ; Nguyen Don J., Buck converter.
  13. Efland Taylor R. ; Skelton Dale J., CMOS power device and method of construction and layout.
  14. Peter Elenius ; Harry Hollack, Chip scale package using large ductile solder balls.
  15. Akram Salman, Conductive bumps on die for flip chip application.
  16. Nickel, Charles, Conductive routings in integrated circuits.
  17. Henze Christopher P. (Eagan MN) Mohan Ned (Minneapolis MN) Hayes John G. (Camarillo CA), Constant frequency resonant power converter with zero voltage switching.
  18. Williams Richard K. (Cupertino CA), Contact geometry for improved lateral MOSFET.
  19. Wilcox Milton E. (Saratoga CA) Flatness Randy G. (Los Gatos CA), Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit.
  20. Wilcox, Milton E.; Flatness, Randy G., Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit.
  21. Littlefield Troy J., Controller circuit for controlling a step down switching regulator operating in discontinuous conduction mode.
  22. Burns Carmen D. (San Jose CA), Copper-to-gold thermal compression gang bonding of interconnect leads to semiconductive devices.
  23. Andersen Brad E. (Dover NJ) Hamilton Billy H. (Summit NJ) Schroeder Robert E. (Flanders NJ), Current flare out limit control for PWM converter.
  24. Fiez Terri S. (Pullman WA) Cooley Gregory M. (Dallas TX) Buchanan Bryan (Gig Harbor WA), DC-to-DC switching power supply utilizing a delta-sigma converter in a closed loop controller.
  25. Saleh Mustafa Y. (Margate FL), DC/DC Converter.
  26. Herandez Jorge M. (1920 E. Jarvis Mesa AZ 85202) Simpson Scott S. (Senexet Rd. Woodstock CT 06281) Hyslop Michael S. (4147 W. Victoria La. Chandler AZ 85226), Device for interconnecting integrated circuit packages to circuit boards.
  27. Efland Taylor R. (Richardson TX) Malhi Satwinder (Garland TX) Smayling Michael C. (Missouri City TX) Devore Joseph A. (Dallas TX) Teggatz Ross E. (Dallas TX) Morton Alec J. (Plano TX), Device having current ballasting and busing over active area using a multi-level conductor process.
  28. Brofman,Peter J.; Farooq,Shaji; Knickerbocker,John U.; Langenthal,Scott I.; Ray,Sudipta K.; Stalter,Kathleen A., Dielectric interposer for chip to substrate soldering.
  29. Boros Victor B. (New York NY) Thau Frederick E. (Teaneck NJ), Digital arrangement for determining average current of a circuit by monitoring a voltage.
  30. Bruckner Ronald L. (Longwood FL) Khamare Ishwar S. (Fern Park FL) Voyer Joseph L. (Longwood FL) Hamilton Rodney V. (Orlando FL) Gheorghiu Paul (Orlando FL), Digital controller.
  31. Miller ; Norman Richards, Digital feedback control utilizing accumulated reference count to regulate voltage output of switching regulator.
  32. Merrill Richard B., Digital feedback power supply.
  33. Katoozi Mehdi (Bellevue WA) La Rue George S. (Bellevue WA), Digital pulse width modulator for power supply control.
  34. McVey Michael J. (Manhattan Beach CA), Digital switching voltage regulator.
  35. Burstein Andrew J. ; Lidsky David B. ; Stratakos Anthony ; Sullivan Charlie ; Clark William, Digital voltage regulator using current control.
  36. Burstein, Andrew J.; Lidsky, David B.; Stratakos, Anthony; Sullivan, Charlie; Clark, William, Digital voltage regulator using current control.
  37. Henze Christopher P. (Eagan MN), Digitally controlled A.C. to D.C. power conditioner.
  38. Vinsant Ronald G. (Mountain View CA) DeFiore John E. (Sunnyvale CA), Digitally controlled switchmode power supply.
  39. Goodfellow,John Ryan; Carroll,Robert T.; Trivedi,Malay; McShane,Erik; Mori,Kevin, Digitally controlled voltage regulator.
  40. George Reed A. (Lake Worth FL) Cheraso John P. (Boynton Beach FL) Hendricks Douglas W. (Boca Raton FL), Direct chip attachment structure and method.
  41. Stratakos Anthony J. ; Lidsky David B. ; Clark William A., Discrete-time sampling of data for use in switching regulations.
  42. Stratakos Anthony J. ; Lidsky David B. ; Clark William A., Discrete-time sampling of data for use in switching regulators.
  43. Shih Yi-Chi (Torrance CA) Wang David C. (Rancho Palos Verdes CA) Le Huy M. (Monterey Park CA) Hwang Vincent (Long Beach CA) Chi Tom Y. (San Gabriel CA), Distributed cell monolithic mircowave integrated circuit (MMIC) field-effect transistor (FET) amplifier.
  44. Baynes Martin J. (Cape Elizabeth ME), Distributed field effect transistor structure.
  45. Blish ; II Richard C., Distributed voltage converter apparatus and method for high power microprocessor with array connections.
  46. Dranchak David William ; Kelleher Robert Joseph ; Pagnani David Peter ; Zippetelli Patrick Robert, Dual substrate package assembly coupled to a conducting member.
  47. Muterspaugh Max W. (Indianapolis IN), Dual voltage voltage regulator with foldback current limiting.
  48. Gottschall Robert A. ; Gregor Roger P. ; Libous James P., Dual-pitch perimeter flip-chip footprint for high integration asics.
  49. Riggio ; Jr. Salvatore R. (Boca Raton FL), Dynamic loop compensator for continuous mode power converters.
  50. Shimer Daniel W. (Danville CA) Lange Arnold C. (Livermore CA), E-beam high voltage switching power supply.
  51. Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX), ESD protection structure using LDMOS diodes with thick copper interconnect.
  52. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  53. Nye ; III Henry A. (Bedford NY) Roeder Jeffrey F. (Brookfield CT) Tong Ho-Ming (Yorktown Heights NY) Totta Paul A. (Poughkeepsie NY), Electroplated solder terminal.
  54. Udomoto Junichi,JPX ; Komaru Makio,JPX, Field effect transistor array including resistive interconnections.
  55. Kanamori Mikio (Tokyo JPX) Imamura Takafumi (Shiga JPX), Field effect transistors having comb-shaped electrode assemblies.
  56. Tihanyi Jeno,DEX ; Strack Helmut,DEX ; Geiger Heinrich,DEX, Field effect-controlled semiconductor component.
  57. Liang Mike, Flip chip bump distribution on die.
  58. Erickson Curt A, Flip chip solder bump pad.
  59. Burstein Andrew J. ; Nickel Charles, Flip-chip switching regulator.
  60. Nagata Takashi,JPX ; Uesugi Hiroshi,JPX ; Tanaka Hiroaki,JPX, Gate array having highly flexible interconnection structure.
  61. Tanaka Yasunori (Yokohama JPX) Sei Toshikazu (Kawasaki JPX) Kobayashi Teruo (Tokyo JPX) Yamada Kaoruko (Yokohama JPX), Gate array semiconductor circuit device, input circuit, output circuit and voltage lowering circuit.
  62. Lane Christopher F., High density integrated circuit pad structures.
  63. Pearce Lawrence George, High efficiency quasi-vertical DMOS in CMOS or BICMOS process.
  64. Joshi Rajeev, High performance flip chip package.
  65. Joshi,Rajeev, High performance multi-chip flip chip package.
  66. Rajeev Joshi, High performance multi-chip flip chip package.
  67. Bird Philip H. (Sidcup GB2) Coe David J. (East Grinstead GB3) Paxman David H. (Redhill GB2) Korteling Aart G. (Waalre NLX), High voltage semiconductor with integrated low voltage circuitry.
  68. Kikinis Dan (Saratoga CA) Lo Thomas (Cupertino CA), Highly efficient rectifying and converting circuit for computer power supplies.
  69. Kinugasa Masanori (Yokohama JPX) Tanaka Fuminari (Tokyo JPX) Shigehara Hiroshi (Yokohama JPX) Ohta Hirokata (Yokohama JPX), Insulated gate type field effect transistor.
  70. Zhao, Lily; Liang, Dexin, Integrated circuit package, ball-grid array integrated circuit package.
  71. Wagenaar Kornelis J. (Nijmegen NLX), Integrated logic circuit having insulated gate field effect transistors.
  72. McMahon John Francis (Phoenix AZ), Kangaroo multi-package interconnection concept.
  73. Ohno Kenichi (Tokyo JPX) Hosomizu Tohru (Yokohama JPX) Ogawa Rokutaro (Yokohama JPX) Shimizu Mitsuhisa (Kawasaki JPX), Large scale semiconductor integrated circuit device.
  74. Jan Tzong-Shi,TWX, Layout of semiconductor devices to increase the packing density of a wafer.
  75. Tan Tat S. (P.O. Box 24 Mt. Marion NY 12456), Linear switching regulator.
  76. Fogg John K. (Durham NC) Utter Wayne (Endicott NY) Dohanich George (Endicott NY), Low voltage DC-to-DC power converter integrated circuit and related methods.
  77. Lau John H., Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips.
  78. Queyssac Daniel G., Low-profile removable ball-grid-array integrated circuit package.
  79. Sasaki Yoshitaka (Yokohama JPX), MOS FET semiconductor device having a cell pattern arrangement for optimizing channel width.
  80. Schultz Aaron ; Burstein Andrew J. ; Christenson Michael, Method and apparatus for control of a power transistor in a digital voltage regulator.
  81. Burstein Andrew J. ; Schultz Aaron, Method and apparatus for digital voltage regulation.
  82. Laplace ; Jr. Carl J. (Covington LA) Williams Conrad F. (New Orleans LA), Method and apparatus for monitoring instantaneous electrical parameters of a power distribution system.
  83. Doluca Tunc (Saratoga CA), Method and apparatus for multiple output regulation in a step-down switching regulator.
  84. Abbondanti Alberto (Penn Hills PA), Method and apparatus for sampling output AC currents in a voltage-fed inverter power supply.
  85. Brown Alan E. ; Swamy N. Deepak, Method and apparatus for voltage regulation within an integrated circuit package.
  86. Efland Taylor R. ; Malhi Satwinder ; Smayling Michael C. ; Devore Joseph A. ; Teggatz Ross E. ; Morton Alec J., Method for current ballasting and busing over active device area using a multi-level conductor process.
  87. Elenius Peter ; Hollack Harry, Method for forming chip scale package.
  88. Sweitzer Brent N. (Nerstrand MN), Method for interconnecting a flip chip to a printed circuit substrate.
  89. Kondo Kenji (Hoi JPX) Kunda Hachiro (Chiryu JPX) Sonobe Toshio (Okazaki JPX), Method for making a semiconductor device.
  90. Kweon Young Do,KRX ; Kim Kwang Soo,KRX, Method for simultaneously manufacturing chip-scale package using lead frame strip with a plurality of lead frames.
  91. Williams Richard K. ; Kasem Mohammad, Method of fabricating lateral power MOSFET having metal strap layer to reduce distributed resistance.
  92. Adams Victor J. (Tempe AZ) Dougherty David J. (Tempe AZ), Method of forming a package assembly.
  93. Duffy,Thomas P.; Goodfellow,John Ryan; Carroll,Robert T.; Cote,Kevin J.; Karikalan,Sampath K. V.; Golwalkar,Suresh, Microelectronic component with reduced parasitic inductance and method of fabricating.
  94. Brunk Manfred (Erlangen/Spardorf DEX) Chluba Gnther (Nrnberg DEX) Dssel Karl-Heinz (Roth DEX), Microprocessor-controlled DC-DC converter.
  95. Gray Richard L., Monolithic power converter with a power switch as a current sensing element.
  96. Rostoker Michael D. (San Jose CA), Multi-chip semiconductor arrangements using flip chip dies.
  97. Wenzel James F. ; DeHaven Robert K. ; Marietta Bryan D. ; Johnston James P., Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces.
  98. Watanabe, Hiroshi; Nakamura, Hiroshi; Shimizu, Kazuhiro; Aritome, Seiichi; Yaegashi, Toshitake; Takeuchi, Yuji; Imamiya, Kenichi; Takeuchi, Ken; Oodaira, Hideko, Nonvolatile semiconductor memory.
  99. Hoshi Akio (Isesaki JPX) Sato Yukihiro (Maebashi JPX) Koda Toyomasa (Takasaki JPX) Yoshida Isao (Tokyo JPX) Sakamoto Kouzou (Hachioji JPX), Packaged semiconductor device having heat dissipation/electrical connection bumps and method of manufacturing same.
  100. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.
  101. Raiser, George F.; Sundahl, Bob; Mahajan, Ravi, Partial underfill for flip-chip electronic packages.
  102. Berg Steven K. (San Jose CA), Phase lead compensation circuit for an integrated switching regulator.
  103. Pearce Lawrence George (Palm Bay FL), Pilot transistor for quasi-vertical DMOS device.
  104. Kitamura, Yasuhiro; Sakakibara, Toshio; Kohno, Kenji; Mizuno, Shoji; Nakayama, Yoshiaki; Maeda, Hiroshi; Iida, Makio; Fujimoto, Hiroshi; Saitou, Mitsuhiro; Imai, Hiroshi; Ban, Hiroyuki, Power MOS transistor for absorbing surge current.
  105. Tonnel Eugne (Meylan FRX) Thomas Gilles (Fontanil Cornillon FRX), Power MOS transistor structure.
  106. Gray Richard L., Power control chip with circuitry that isolates switching elements and bond wires for testing.
  107. Lee James (Monterey Park CA), Power converter apparatus having instantaneous commutation switching system.
  108. Henze Christopher P. (Eagan MN), Power converter with duty ratio quantization.
  109. Smith David A. (Kowloon HKX) Stewart Neal G. (Sai Kung HKX), Power converters with improved switching efficiency.
  110. Rodov Vladimir ; Hsueh Wayne Y. W. ; Chang Paul ; Chern Michael, Power rectifier device and method of fabricating power rectifier devices.
  111. Dhong Sang H. (Mahopac NY) Shin Hyun J. (Mahopac NY) Hwang Wei (Armonk NY), Power supply tracking regulator for a memory array.
  112. Appeltans Koen E. J. (Eindhoven NLX), Power supply with improved efficiency, transmitter comprising such a power supply.
  113. DeVale Donald P., Primary regulator for an unregulated linear power supply and method.
  114. Su, Chao-Yuan, Process for bonding solder bumps to a substrate.
  115. Kosiak Walter K. (Kokomo IN) Schnabel Douglas R. (Kokomo IN) Mann Jonathan D. (Kokomo IN) Parrish Jack D. (Kokomo IN) Rowlands ; III Paul R. (Kokomo IN), Process for forming high and low voltage CMOS transistors on a single integrated circuit chip.
  116. Kosiak Walter K. (Kokomo IN) Schnabel Douglas R. (Kokomo IN) Mann Jonathan D. (Kokomo IN) Parrish Jack D. (Kokomo IN) Rowlands ; III Paul R. (Kokomo IN), Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip.
  117. Zandman Felix ; Kasem Y. Mohammed ; Ho Yueh-Se, Process of fabricating a chip scale surface mount package for semiconductor device.
  118. Henze Christopher P. (Eagan MN), Quantized duty ratio power sharing converters.
  119. Russell Ernest J. (Richmond TX), Reduced capacitance lead frame for lead on chip package.
  120. Dordi Yezdi N., Reflow ball grid array assembly.
  121. Gaertner Robert F. (San Marcos TX), Regulated dual DC power supply.
  122. Ikeda Shuji (5-15-3 ; Midori-cho Koganei-shi ; Tokyo JPX) Meguro Satoshi (2196-662 ; Hirai Hinode-machi JPX) Hashiba Soichiro (2-14-3 ; Sakaecho Hamura-machi ; Nishitama-gun ; Tokyo JPX) Kuramoto Isa, SRAM with dual word lines overlapping drive transistor gates.
  123. Jin Ho Tae (Suwon ; KRX) Hong In Pyo (Suwon ; KRX) Ko Chang Eui (Suwon ; KRX), Semiconductor chip package using improved tape mounting.
  124. Stager Mark P. ; Yee Abraham F. ; Padmanabhan Gobi R., Semiconductor chip package with interconnect layers and routing and testing methods.
  125. Asami Fumitaka (Kunitachi JPX) Udo Shinya (Kawasaki JPX), Semiconductor delay circuit device.
  126. Maeda Hiroshi (Reutlingen DEX) Ueda Susumu (Nukata-gun JPX) Fujimoto Hiroshi (Nagoya JPX) Nakayama Yoshiaki (Nukata-gun JPX), Semiconductor device.
  127. Ishii Koji,JPX, Semiconductor device and method of fabricating the same.
  128. Hosomi Eiichi,JPX ; Takubo Chiaki,JPX ; Tazawa Hiroshi,JPX ; Shibasaki Koji,JPX, Semiconductor device having a bump electrode connected to an inner lead.
  129. Schaffer,Christopher P.; Cheah,Chuan; Hu,Kevin, Semiconductor device module with flip chip devices on a common lead frame.
  130. Kimura Masakazu,JPX, Semiconductor devices with load elements.
  131. Arakawa Takahiko (Itami JPX), Semiconductor integrated circuit and method of fabricating same and method of arranging cells.
  132. Hamamoto Takeshi (Hyogo JPX) Kobayashi Toshifumi (Hyogo JPX) Yamagata Tadato (Hyogo JPX) Mihara Masaaki (Hyogo JPX), Semiconductor integrated circuit device having improved stacked capacitor and manufacturing method therefor.
  133. Kohno Fumihiro,JPX, Semiconductor memory device, method of laying out semiconductor memory device, method of driving semiconductor pattern of semiconductor device.
  134. Sicard Thierry,FRX ; Machuga Steve Charles,DEX ; Monroe Conrad,DEX, Semiconductor power device.
  135. Leas James M. (South Burlington VT) Koss Robert W. (Burlington VT) Walker George F. (New York NY) Perry Charles H. (Poughkeepsie NY) Van Horn Jody J. (Underhill VT), Semiconductor wafer test and burn-in.
  136. Stratakos Anthony ; Burstein Andrew J. ; Lidsky David B. ; Nguyen Phong ; Clark William, Sensors for measuring current passing through a load.
  137. Dustin Wood ; Seng Hooi Ong ML; Edward A. Burton, Stitched plane structure and process for package power delivery and dual referenced stripline I/O performance.
  138. Clark William A., Switched capacitor current source for use in switching regulators.
  139. Van Buul Marinus C. W. (Breda NLX), Switched voltage converter.
  140. Bonte Anthony K. (Campbell CA) Nelson Carl T. (San Jose CA), Switching regulator circuit using magnetic flux-sensing.
  141. Bonte Anthony K. (Campbell CA) Nelson Carl T. (San Jose CA), Switching regulator circuit using magnetic flux-sensing.
  142. Boros ; Victor Bert, Switching regulator control utilizing digital comparison techniques to pulse width modulate conduction through a switch.
  143. Schultz, Aaron M.; Burstein, Andrew J.; Lidsky, David B.; Stratakos, Anthony J., Switching regulator with capacitance near load.
  144. Mammano Robert A. (Costa Mesa CA) O\Connor John A. (Merrimack NH), Switching regulator with improved Dynamic response.
  145. Marco A. Zuniga ; Charles Nickel, Switching regulator with multiple power transistor driving voltages.
  146. Goodfellow, Ryan; Susak, David, System and method for current sensing.
  147. Duffy, Thomas P.; Goodfellow, Ryan; Trivedi, Malay; Mori, Kevin; Tang, Benjamim, System, device and method for providing voltage regulation to a microelectronic device.
  148. Holzinger Steven T. (Tempe AZ) Barker Larry W. (Chandler AZ), Tape automated bonding and method of making the same.
  149. Iyer Venkat (Santa Clara CA) Belani Jagdish (Cupertino CA) Takiar Hem P. (Fremont CA) Pendse Rajenda (Sunnyvale CA), Tape automated bonding of bumped tape on bumped die.
  150. Eichelberger Charles W. (1256 Waverly Pl. Schenectady NY 12308), Three-dimensional multichip module systems.
  151. Andrew J. Burstein ; Charles Nickel, Transistor pattern for voltage regulator.
  152. Chen Zhi Quan, Two-parts ferroelectric RAM.
  153. Robertson David H. ; Singer Lawrence, Two-phase boosted CMOS switch drive technique and circuit.
  154. Canter Stanley, Voltage converter with battery discharge protection.
  155. Tetsuya Kaneko JP; Junichi Okamura JP, Voltage generator for semiconductor device.
  156. Burstein Andrew J. ; Schultz Aaron, Voltage regulation using an estimated current.
  157. Ito Makoto (Yokohama JPX), Voltage regulator circuit.
  158. Ang Michael Anthony ; Taylor Alexander Dougald, Voltage regulator circuit for attenuating inductance-induced on-chip supply variations.

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  2. Leong, Poh Boon, Combining signal power using magnetic coupling between conductors.
  3. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  4. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  5. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  6. Desbiens, Donald J.; Polhemus, Gary D.; Carroll, Robert T., Electrical connectivity for circuit applications.
  7. Carroll, Robert T., Electrical connectivity of die to a host substrate.
  8. Zhang, Xiaotian; Mallikarjunaswamy, Shekar; Niu, Zhiqiang; Oh, Cheow Khoon; Ho, Yueh-Se, Power device and preparation method thereof.
  9. Michael, Mihalis; Tan, Kwang Hong; Jergovic, Ilija; Chiang, Chiteh; Stratakos, Anthony, Power management applications of interconnect substrates.
  10. Michael, Mihalis; Tan, Kwang Hong; Jergovic, Ilija; Chiang, Chiteh; Stratakos, Anthony, Power management applications of interconnect substrates.
  11. Kaneko, Kishou; Inoue, Naoya; Hayashi, Yoshihiro, Semiconductor device.
  12. Kaneko, Kishou; Inoue, Naoya; Hayashi, Yoshihiro, Semiconductor device and SiP device using the same.
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