Apparatus and associated systems, methods and computer program products relate to using information stored in a flash memory to adjust the operating voltage supplied to the flash memory. The voltage information indicates a minimum operating voltage at which to operate the flash memory device. In gen
Apparatus and associated systems, methods and computer program products relate to using information stored in a flash memory to adjust the operating voltage supplied to the flash memory. The voltage information indicates a minimum operating voltage at which to operate the flash memory device. In general, operating a flash memory device near a minimal operating voltage may substantially minimize power consumption. The minimum operating voltage for individual flash memory devices may vary from IC to IC, by manufacturing lot, and by manufacturer. In a product, the minimum operating voltage for a particular flash memory may be determined, for example, by a controller built-in to a flash memory reporting (automatically or in response to a query) the minimum operating voltage (e.g., 2.5 V, 3.15 V) to a memory controller or microprocessor. The stored voltage information may further include information to adjust the operating voltage based on temperature.
대표청구항▼
1. A flash memory device, comprising: a first plurality of memory cells for storing data;a second plurality of memory cells for storing data;a voltage input adapted for connection to an output of a voltage-regulated power supply;a first register containing information indicating a first minimum oper
1. A flash memory device, comprising: a first plurality of memory cells for storing data;a second plurality of memory cells for storing data;a voltage input adapted for connection to an output of a voltage-regulated power supply;a first register containing information indicating a first minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of the first plurality of memory cells;a second register containing information indicating a second minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of the second plurality of memory cells; anda processor configured to i) identify a greatest minimum operating voltage from among the first minimum operating voltage and the second minimum operating voltage, and ii) determine a selected operating voltage to supply from the voltage-regulated power supply to the voltage input for performing the read operation of the one or more of the first plurality of memory cells based upon the identified greatest minimum operating voltage. 2. The flash memory device of claim 1, further comprising: a temperature sensor configured to measure a temperature associated with the first plurality of memory cells; andwherein the processor is configured to further determine the selected operating voltage to supply from the voltage-regulated power supply to the voltage input for performing the read operation of the one or more of the first plurality of memory cells based upon the temperature measured by the temperature sensor. 3. The flash memory device of claim 1, wherein the processor is further configured to determine the selected operating voltage in response to a start-up of the flash memory device, in response to receiving a read command or a write command for the first plurality of memory cells, or on a recurring basis during operation of the flash memory device. 4. The flash memory device of claim 1, wherein the processor is configured to further determine the selected operating voltage based upon a voltage margin above the greatest minimum operating voltage for reliably operating at least the first memory cells. 5. The flash memory device of claim 4, wherein the voltage margin is based at least in part upon circuit load dynamics associated with at least the first plurality of memory cells. 6. The flash memory device of claim 4, wherein the voltage margin is based at least in part upon a capacitance associated with at least the first plurality of memory cells. 7. The flash memory device of claim 4, wherein the voltage margin is based at least in part upon transient response characteristics associated with the power supply. 8. A method of supplying power to a flash memory device, the method comprising: receiving information indicating a first minimum operating voltage to supply from a voltage-regulated power supply to a voltage input for performing a read operation on one or more of a first plurality of memory cells;receiving information indicating a second minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of a second plurality of memory cells;receiving a command to read data that is stored in the first plurality of memory cells of the flash memory device;selecting a greatest minimum operating voltage from among the first minimum operating voltage and the second minimum operating voltage;setting an output voltage from the voltage-regulated supply to the voltage input for performing the command to read data based upon the received information indicating the first minimum operating voltage and based upon the selected greatest minimum operating voltage; andexecuting the command to read the data using the set output voltage. 9. The method of claim 8, wherein the output voltage is further set based upon a voltage margin above the greatest minimum operating voltage for reliably operating at least the first memory cells. 10. The method of claim 9, wherein the voltage margin is based at least in part upon circuit load dynamics associated with at least the first memory cells. 11. The method of claim 9, wherein the voltage margin is based at least in part upon a capacitance associated with at least the first memory cells. 12. The method of claim 9, wherein the voltage margin is based at least in part upon transient response characteristics associated with the power supply. 13. The method of claim 8, further comprising: receiving a temperature measurement associated with the first plurality of memory cells; andwherein the output voltage is further set based upon the received temperature measurement. 14. The method of claim 8, wherein setting the output voltage is further performed in response to the flash memory device starting-up or on a recurring basis during operation of the flash memory device. 15. A computer program product tangibly embodied in a machine-readable storage device, the computer program product containing instructions that, when executed, cause a processor to perform operations to supply power to a flash memory device, the operations comprising: receiving information indicating a first minimum operating voltage to supply from a voltage-regulated power supply to a voltage input for performing a read operation on one or more of a first plurality of memory cells;receiving information indicating a second minimum operating voltage to supply from the voltage-regulated power supply to the voltage input for performing a read operation on one or more of a second plurality of memory cells;receiving a command to read data that is stored in the first plurality of memory cells of the flash memory device;selecting a greatest minimum operating voltage from among the first minimum operating voltage and the second minimum operating voltage;sending a signal to the voltage-regulated supply to supply an output voltage to the voltage input for performing the command to read data, wherein the output voltage is determined based upon the selected greatest minimum operating voltage; andexecuting the command to read the data using the set output voltage. 16. The computer program product of claim 15, wherein the output voltage is further determined based upon a voltage margin above the greatest minimum operating voltage for reliably operating at least the first memory cells. 17. The computer program product of claim 16, wherein the voltage margin is based at least in part upon circuit load dynamics associated with at least the first memory cells. 18. The computer program product of claim 16, wherein the voltage margin is based at least in part upon a capacitance associated with at least the first memory cells. 19. The computer program product of claim 16, wherein the voltage margin is based at least in part upon transient response characteristics associated with the power supply. 20. The computer program product of claim 15, wherein the operations further comprise: receiving a temperature measurement associated with the first plurality of memory cells; andwherein the output voltage is further determined based upon the received temperature measurement.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (74)
Jacobs,Daniel G.; Castleberry,James E., ATA device control via a packet-based interface.
Krenzke,Rainer; Ji,Cang, Accurate power supply system for flash-memory including on-chip supply voltage regulator, reference voltage generation, power-on reset, and supply voltage monitor.
Sinderson Richard L. (Pearland TX) Salazar George A. (Friendswood TX) Haddick ; Jr. Clyde M. (Friendship TX) Spahn Caroll J. (Houston TX) Venkatesh Chikkabelarangala N. (Friendswood TX), Adaptive data acquisition multiplexing system and method.
Fandrich Mickey L. (Placerville CA) Kynett Virgil N. (El Dorado Hills CA) Robinson Kurt (Newcastle CA), Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory.
Cases,Moises; de Araujo,Daniel N.; Pham,Nam Huu; Roumbakis,Menas, Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress.
Wallace, Robert F.; Norman, Robert D.; Harari, Eliyahou, Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems.
Kevin M. Conley ; John S. Mangan ; Jeffrey G. Craig, Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks.
Peter Wung Lee ; Hsing-Ya Tsao TW; Fu-Chang Hsu TW; Wen-Tan Fan TW, Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation.
Janzen,Jeffery W.; Schaefer,Scott; Farrell,Todd D., Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices.
Naveh,Alon; Surgutchik,Roman; Gunther,Stephen H.; Greiner,Robert; Ma,Hung Piao; Dai,Kevin; Wong,Keng, Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device.
Sedlak Holger,DEX ; Viehmann Hans-Heinrich,DEX, Method and device for automatic determination of the required high voltage for programming/erasing an EEPROM.
Fandrich Mickey L. (Placerville CA) Fedel Salim B. (Folsom CA) Price Thomas C. (Fair Oaks CA) Durante Richard J. (Citrus Heights CA) Gould Geoffrey A. (El Dorado Hills CA) Goodell Timothy W. (Elk Gro, Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block.
Wells Steven E. (Citrus Heights CA) Magnusson Eric J. (Orangevale CA) Hasbun Robert N. (Shingle Springs CA), Method of managing defects in flash disk memories.
Wells Steven E. (Citrus Heights CA) Magnusson Eric J. (Orangevale CA) Hasbun Robert N. (Shingle Springs CA), Method of managing defects in flash disk memories.
Ellsworth Earle ; Evans Laura Hepner ; Ghoman Sangram Singh ; Garcia Enrique Quique ; Jarvis Thomas Charles ; Kalos Matthew Joseph ; O'Neill Ralph ; Phan Lisa ; Schreiber David Brent, Programmable hardware mailbox message technique and system.
Cernea Raul-Adrian (Cupertino CA) Lee Douglas J. (San Jose CA) Mofidi Mehrdad (Fremont CA) Mehrotra Sanjay (Milpitas CA), Programmable power generation circuit for flash EEPROM memory systems.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.