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Instruction set design, control and communication in programmable microprocessor cores and the like

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/30
출원번호 US-0156007 (2008-05-29)
등록번호 US-8181003 (2012-05-15)
발명자 / 주소
  • Wang, Xiaolin
  • Wu, Qian
  • Marshall, Benjamin
  • Wang, Fugui
  • Pitarys, Gregory
  • Ning, Ke
출원인 / 주소
  • Axis Semiconductor, Inc.
대리인 / 주소
    Maines Cernota & Rardin
인용정보 피인용 횟수 : 1  인용 특허 : 39

초록

Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has

대표청구항

1. A method of clock cycle synchronized flexible programmable execution of a data processing program, the method comprising: providing a processor containing a plurality of functional units, each functional unit being a computation unit, memory unit, full access switch unit for interconnecting execu

이 특허에 인용된 특허 (39)

  1. Iwata Eiji (Tokyo JPX), Adaptive video signal processing apparatus.
  2. Krech, Jr., Alan S.; Jordan, Stephen D, Algorithmically programmable memory tester with history FIFO's that aid in error analysis and recovery.
  3. Hastie,Neil S., Controlling out of order execution pipelines issue tagging.
  4. DeHon Andre ; Bolotski Michael ; Knight ; Jr. Thomas F., DPGA-coupled microprocessors.
  5. Schultz, Jr.,John C. F.; Crawford,Lawrence Griffin, Distributed matrix switch.
  6. Ing-Simmons Nicholas K. (Oakley TX GB2) Guttag Karl M. (Missouri City TX) Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2), Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode.
  7. Lin,Tay Jyi; Jen,Chein Wei; Liu,Chih Wei; Huang,Po Han; Huang,Wei Sheng; Chang,Chan Hao, Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer.
  8. Stiehl, Gregory J.; Anderson, David L.; Everitt, Cass W.; French, Mark J.; Molnar, Steven E., Hierarchical multi-precision pipeline counters.
  9. Pechanek Gerald G. ; Kurak ; Jr. Charles W., Manifold array processor.
  10. Lauritzen Mogens ; Weiss Richard A., Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction.
  11. Fukuda, Hiroaki; Namizuka, Yoshiyuki; Miyazaki, Shinya; Oteki, Sugitaka; Satoh, Takako; Ishii, Rie; Tone, Takeharu; Kawamoto, Hiroyuki; Miyazaki, Hideto; Yoshizawa, Fumio; Takahashi, Yuji; Nomizu, Ya, Method and apparatus for image processing, and a computer product.
  12. Fukuda,Hiroaki; Namizuka,Yoshiyuki; Miyazaki,Hideto; Miyazaki,Shinya; Nomizu,Yasuyuki; Oteki,Sugitaka; Satoh,Takako; Tone,Takeharu; Yoshizawa,Fumio; Takahashi,Yuji; Kawamoto,Hiroyuki; Ishii,Rie, Method and apparatus for image processing, and a computer product.
  13. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
  14. Gerald G. Pechanek ; Juan Guillermo Revilla ; Edwin F. Barry, Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor.
  15. Pechanek Gerald G. ; Revilla Juan Guillermo ; Barry Edwin F., Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor.
  16. Pechanek, Gerald G.; Revilla, Juan Guillermo; Barry, Edwin Franklin, Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor.
  17. Pechanek, Gerald George; Drabenstott, Thomas L.; Revilla, Juan Guillermo; Strube, David; Morris, Grayson, Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication.
  18. Gerald G. Pechanek ; Thomas L. Drabenstott ; Juan Guillermo Revilla ; David Carl Strube ; Grayson Morris, Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication.
  19. Pechanek Gerald G. ; Drabenstott Thomas L. ; Revilla Juan Guillermo ; Strube David Carl ; Morris Grayson, Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication.
  20. Kasahara,Eiji, Methods and apparatus for improving processing performance by controlling latch points.
  21. Barry, Edwin Frank; Pechanek, Gerald G., Methods and apparatus for loading a very long instruction word memory.
  22. Barry, Edwin Frank; Pechanek, Gerald G., Methods and apparatus for loading a very long instruction word memory.
  23. Pechanek Gerald G. ; Barry Edwin F. ; Revilla Juan Guillermo ; Larsen Larry D., Methods and apparatus for scalable instruction set architecture with dynamic compact instructions.
  24. Revilla Juan Guillermo ; Barry Edwin F. ; Marchand Patrick Rene ; Pechanek Gerald G., Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor.
  25. Gupta Rajiv ; Raje Prasad, Microprocessor having software controllable power consumption.
  26. Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX), Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD).
  27. Gove Robert J. (Plano TX) Guttag Karl M. (Missouri City TX) Balmer Keith (Bedfordshire GB2) Ing-Simmons Nicholas K. (Bedfordshire GB2), Multi-processor with crossbar link of processors and memories and method of operation.
  28. Pappalardo,Francesco; Pennisi,Agatino, Pipeline structure.
  29. Lee Sherman ; Kyle David G., Port for fine tuning a central processing unit.
  30. Yoshikawa, Takashi; Asano, Shigehiro; Yamada, Yutaka, Processing in pipelined computing units with data line and circuit configuration rule signal line.
  31. Atsushi Sakurai,JPX, Processor having a variable number of stages in a pipeline.
  32. Rupp Charle R., Reconfigurable computer architecture for use in signal processing applications.
  33. Smith Stephen J., Reconfigurable computer architecture using programmable logic devices.
  34. Ledzius, Robert C.; Flemmons, James L.; Maturo, Lawrence R., Reconfigurable computing system and method and apparatus employing same.
  35. Balmer Keith (6 Salcombe Close Bedford (Bedfordshire) GB2 MK40 38A) Ing-Simmons Nicholas K. (74 Lincroft ; Oakley Bedford (Bedfordshire) TX GB2 MK43 7SS) Guttag Karl M. (4015 S. Sandy Ct. Missouri Ci, Switch matrix having integrated crosspoint logic and method of operation.
  36. Gove Robert J. ; Balmer Keith,GBX ; Ing-Simmons Nicholas Kerin,GBX ; Guttag Karl Marion, System and method of memory access in apparatus having plural processors and plural memories.
  37. Norden, Erik K.; Arnold, Roger D.; Ober, Robert E.; Hastie, Neil S., Variable length instruction pipeline.
  38. Norden,Erik K.; Arnold,Roger D.; Ober,Robert E.; Hastie,Neil S., Variable length instruction pipeline.
  39. Carnevale Michael J. (Rochester MN) Kalla Ronald N. (Zumbro Falls MN) McClannahan Gary P. (Rochester MN) Trombley Michael R. (Rochester MN), Variable stage entry/exit instruction pipeline.

이 특허를 인용한 특허 (1)

  1. Dimond, Robert Gwilym, Systems and methods for reducing logic switching noise in parallel pipelined hardware.
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