Integrated circuit device and electronic instrument
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/62
H02H-009/00
G02B-006/26
출원번호
US-0703686
(2007-02-08)
등록번호
US-8188545
(2012-05-29)
우선권정보
JP-2006-034518 (2006-02-10)
발명자
/ 주소
Saiki, Takayuki
Ito, Satoru
Moriguchi, Masahiko
출원인 / 주소
Seiko Epson Corporation
대리인 / 주소
Oliff & Berridge, PLC
인용정보
피인용 횟수 :
1인용 특허 :
104
초록▼
A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a
A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.
대표청구항▼
1. A semiconductor integrated circuit having a first side, a second side, a third side and a fourth side, the first side being shorter than the second side, the third side being shorter than the fourth side, the first side being opposite to the third side, the second side being opposite to the fourt
1. A semiconductor integrated circuit having a first side, a second side, a third side and a fourth side, the first side being shorter than the second side, the third side being shorter than the fourth side, the first side being opposite to the third side, the second side being opposite to the fourth side, a first direction being a direction from the first side toward the third side, and a second direction being a direction from the second side toward the fourth side, the semiconductor integrated circuit comprising: a first interface region provided along the fourth side of the semiconductor integrated circuit, the first interface region including a plurality of first pads arranged in the first direction in a plan view, the first interface region including a plurality of second pads arranged in the first direction in a plan view, a row of the plurality of first pads being positioned between the fourth side of the semiconductor integrated circuit and a row of the plurality of second pads in a plan view;a second interface region provided along the second side, the second interface region including a plurality of third pads arranged in the first direction in a plan view; anda plurality of circuit blocks positioned between the first interface region and the second interface region, the plurality of circuit blocks being arranged in the first direction in a plan view,the plurality of circuit blocks including a data driver block that drives at least a data line of a display panel, the data driver block including at least a data latch circuit, a D/A conversion circuit, and an operational amplifier,no other circuit blocks of the plurality of circuit blocks being positioned between the data driver block and the first interface region in the second direction in a plan view,no other circuit blocks of the plurality of circuit blocks being positioned between the data driver block and the second interface region in the second direction in a plan view,one of the plurality of first pads having an approximately rectangular shape having a long side along the second direction and a short side along the first direction in a plan view,the one of the plurality of first pads being electrically connected with a first one of a plurality of electronic discharge protection elements and a second one of the plurality of electronic discharge protection elements, the first one of the plurality of electronic discharge protection elements being electrically connected with a first power supply line and the one of the plurality of first pads, the second one of the plurality of electronic discharge protection elements being electrically connected with a second power supply line and the one of the plurality of first pads,at least a part of the first one of the plurality of electronic discharge protection elements and at least a part of the second one of the plurality of electronic discharge protection elements being positioned underneath the one of the plurality of first pads,an impurity layer of at least one of the first one of the plurality of electronic discharge protection elements and the second one of the plurality of electronic discharge protection elements having a shape in which a dimension in the first direction is greater than a dimension in the second direction. 2. The semiconductor integrated circuit as defined in claim 1, the first one of the plurality of electronic discharge protection elements being positioned underneath a region of the row of the plurality of first pads in a plan view,the second one of the plurality of electronic discharge protection elements being positioned underneath a region of the row of the plurality of first pads in a plan view,a third one of the plurality of electronic discharge protection elements being electrically connected with the one of the plurality of second pads, the third one of the plurality of electronic discharge protection elements and the first one of the plurality of electronic discharge protection elements being arranged in the first direction in a plan view,a fourth one of the plurality of electronic discharge protection elements being electrically connected with the one of the plurality of second pads, the fourth one of the plurality of electronic discharge protection elements and the second one of the plurality of electronic discharge protection elements being arranged in the first direction in a plan view. 3. The semiconductor integrated circuit as defined in claim 2, a well in which the first one of the plurality of electronic discharge protection elements is formed and a well in which the third one of the plurality of electronic discharge protection elements is formed arranged in the first direction in a plan view,a well in which the second one of the plurality of electronic discharge protection elements is formed and a well in which the fourth one of the plurality of electronic discharge protection elements is formed arranged in the first direction in a plan view,the well in which the first one of the plurality of electronic discharge protection elements is formed and the well in which the third one of the plurality of electronic discharge protection elements is formed being separated in the first direction in a plan view. 4. The semiconductor integrated circuit as defined in claim 2, the second one of the plurality of electronic discharge protection elements being disposed in a triple well in a plan view. 5. The semiconductor integrated circuit as defined in claim 1, the impurity layer of the first one of the plurality of electronic discharge protection elements being formed in a shape of a ring in a plan view. 6. The semiconductor integrated circuit as defined in claim 1, a power supply protection element being positioned between the first and second power supply lines. 7. The semiconductor integrated circuit as defined in claim 6, the plurality of circuit blocks including: a RAM which stores data displayed on a display panel, the RAM having a bitline protection interconnect layer which protects a bitline, the bitline protection interconnect layer being electrically connected with the second power supply line and the power supply protection element. 8. The semiconductor integrated circuit as defined in claim 1, the plurality of first pads being arranged at an equal pitch along the first direction, the row of the plurality of first pads and the row of the plurality of second pads adjacently disposed in the second direction in a plan view, the row of the plurality of first pads and the row of the plurality of second pads being shifted in the first direction by a half pitch of the equal pitch. 9. An electronic instrument comprising: the semiconductor integrated circuit as defined in claim 1,the display panel having the data line. 10. A semiconductor integrated circuit having a first side, a second side, a third side and a fourth side, the first side being shorter than the second side, the third side being shorter than the fourth side, the first side being opposite to the third side, the second side being opposite to the fourth side, a first direction being a direction from the first side toward the third side, and a second direction being a direction from the second side toward the fourth side, the semiconductor integrated circuit comprising: a first interface region provided alongside the fourth side of the semiconductor integrated circuit, the first interface region including a plurality of first pads arranged in the first direction in a plan view, the first interface region including a plurality of second pads arranged in the second direction in a plan view, a row of the plurality of first pads being positioned between the fourth side of the semiconductor integrated circuit and a row of the plurality of second pads in a plan view;a second interface region provided along the second side, the second interface region including a plurality of third pads arranged in the first direction in a plan view; anda plurality of circuit blocks positioned between the first interface region and the second interface region, the plurality of circuit blocks being arranged in the first direction in a plan view,the plurality of circuit blocks including a data driver block that drives at least a data line of a display panel, the data driver block including at least a data latch circuit and a D/A conversion circuit,no other circuit blocks of the plurality of circuit blocks being positioned between the data driver block and the first interface region in the second direction in a plan view,no other circuit blocks of the plurality of circuit blocks being positioned between the data driver block and the second interface region in the second direction in a plan view,one of the plurality of first pads having an approximately rectangular shape having a long side along the second direction and a short side along the first direction in a plan view,the one of the plurality of first pads being electrically connected with a first one of a plurality of electronic discharge protection elements and a second one of the plurality of electronic discharge protection elements, the first one of the plurality of electronic discharge protection elements being electrically connected with a first power supply line and the one of the plurality of first pads, the second one of the plurality of electronic discharge protection elements being electrically connected with a second power supply line and the one of the plurality of first pads,the one of the plurality of first pads being formed in an approximately rectangular shape having a long side along the second direction and a short side along the first direction,at least a part of the first one of the plurality of electronic discharge protection elements and at least a part of the second one of the plurality of electronic discharge protection elements being positioned underneath the one of the plurality of first pads. 11. The semiconductor integrated circuit as defined in claim 10, a third one of the plurality of electronic discharge protection elements being electrically connected with the one of the plurality of second pads, the third one of the plurality of electronic discharge protection elements and the first one of the plurality of electronic discharge protection elements being arranged in the first direction in a plan view,a fourth one of the plurality of electronic discharge protection elements being electrically connected with the one of the plurality of second pads, the fourth one of the plurality of electronic discharge protection elements and the second one of the plurality of electronic discharge protection elements being arranged in the first direction in a plan view,the first one of the plurality of electronic discharge protection elements and the second one of the plurality of electronic discharge protection elements forming a first pair, the third one of the plurality electronic discharge protection elements and the fourth one of the plurality of electronic discharge protection elements forming a second pair, the first pair and the second pair being mirror-image disposed with respect to an axis parallel to the first direction in a lower layer of the row of the plurality of first pads in a plan view. 12. The semiconductor integrated circuit as defined in claim 11, outermost pads of the plurality of first pads in the first direction in a plan view electrically connected with the first one of the plurality of electronic discharge protection elements first and the second one of the plurality of electronic discharge protection elements positioned in a lower layer of the outermost pads of the plurality of first pads. 13. The semiconductor integrated circuit as defined in claim 10, the plurality of circuit blocks including: a scan driver which drives a scan line of a display panel, the one of the plurality of first pads being electrically connected with an output line of the scan driver. 14. An electronic instrument comprising: the semiconductor integrated circuit as defined in claim 10,the display panel having the data line. 15. A semiconductor integrated circuit having a first side, a second side, a third side and a fourth side, the first side being shorter than the second side, the third side being shorter than the fourth side, the first side being opposite to the third side, the second side being opposite to the fourth side, a first direction being a direction from the first side toward the third side, and a second direction being a direction from the second side toward the fourth side, the semiconductor integrated circuit comprising: a first interface region provided alongside the fourth side of the semiconductor integrated circuit, the first interface region including a plurality of first pads arranged in the first direction in a plan view, the first interface region including a plurality of second pads arranged in the second direction in a plan view, a row of the plurality of first pads being positioned between the fourth side of the semiconductor integrated circuit and a row of the plurality of second pads in a plan view;a second interface region provided along the second side, the second interface region including a plurality of third pads arranged in the first direction in a plan view; anda plurality of circuit blocks positioned between the first interface region and the second interface region, the plurality of circuit blocks being arranged in the first direction in a plan view,one of the plurality of first pads having an approximately rectangular shape having a long side along the second direction and a short side along the first direction in a plan view,the one of the plurality of first pads being electrically connected with a first one of a plurality of electronic discharge protection elements and a second one of the plurality of electronic discharge protection elements, the first one of the plurality of electronic discharge protection elements being electrically connected with a first power supply line and the one of the plurality of first pads, the second one of the plurality of electronic discharge protection elements being electrically connected with a second power supply line and the one of the plurality of first pads,at least a part of the first one of the plurality of electronic discharge protection elements and at least a part of the second one of the plurality of electronic discharge protection elements being positioned underneath the one of the plurality of first pads,an impurity layer of at least one of the first one of the plurality of electronic discharge protection elements and the second one of the plurality of electronic discharge protection elements having a shape in which a dimension in the first direction is greater than a dimension in the second direction. 16. An electronic instrument comprising: the semiconductor integrated circuit as defined in claim 15, anda display panel having a data line.
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