최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0840742 (2010-07-21) |
등록번호 | US-8195856 (2012-06-05) |
우선권정보 | DE-196 54 595 (1996-12-20) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 542 |
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (fo
A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
1. A data processor chip comprising: a plurality of programmable data processing arrangements;a segmented bus system including a plurality of segments that are adapted for simultaneous transmission on at least two of the plurality of segments, and that are adapted for interconnecting the plurality o
1. A data processor chip comprising: a plurality of programmable data processing arrangements;a segmented bus system including a plurality of segments that are adapted for simultaneous transmission on at least two of the plurality of segments, and that are adapted for interconnecting the plurality of programmable data processing arrangements;at least one data cache arrangement that: is adapted for connection to the plurality of programmable data processing arrangements via at least a subset of the plurality of segments; andincludes an arbiter adapted to select, for each of a plurality of data transmissions, at least one respective one of the plurality of segments for a respective connection to one or more of the plurality of programmable data processing arrangements; andat least one permanently implemented memory interface unit that is adapted for transferring data between the at least one data cache and; a higher level memory. 2. The data processor chip according to claim 1, wherein the higher level memory is a Synchronous DRAM memory. 3. The data processor chip according to claim 1, wherein the higher level memory is a RAMBUS memory. 4. The data processor chip according to claim 1, wherein the higher level memory is a synchronous memory. 5. The data processor chip according to claim 4, wherein the synchronous memory is a Synchronous DRAM memory. 6. The data processor chip according to claim 4, wherein the synchronous memory is a RAMBUS memory.
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