Dual side cooling integrated power device module and methods of manufacture
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0836664
(2010-07-15)
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등록번호 |
US-8198134
(2012-06-12)
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발명자
/ 주소 |
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출원인 / 주소 |
- Fairchild Semiconductor Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
1 인용 특허 :
4 |
초록
▼
An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached res
An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.
대표청구항
▼
1. A method of making an integrated transistor module comprising: providing a planar lead frame having first and second spaced pads, one or more common source-drain leads located between said pads and one or more drain leads located on the outside of said second pad;flip chip attaching first and sec
1. A method of making an integrated transistor module comprising: providing a planar lead frame having first and second spaced pads, one or more common source-drain leads located between said pads and one or more drain leads located on the outside of said second pad;flip chip attaching first and second transistors respectively to said first and second pads, each transistor having source, gate and drain electrodes, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads;attaching a first clip to the drain of said first transistor and electrically connecting said first clip to said one or more common source-drain leads, said first clip having a planar member;attaching a second clip to the drain of said second transistor and electrically connecting said second clip to said one or more drain leads located on the outside of said second pad, said second clip having a planar member; andpartially encapsulating in molding material said planar lead frame, said transistors, and said clips with a portion of bottom surfaces of each of said first and second pads and said planar members of said clips being exposed to provide dual cooling of said integrated transistor module. 2. The method of claim 1 wherein said pads of the lead frame and said clips are exposed and free from molding material to provide dual cooling of said module. 3. The method of claim 1 wherein said first and second transistors are metal oxide semiconductor field effect transistors (MOSFET). 4. The method of claim 1 wherein said first and second transistors are respectively high side and low side power transistors that are components of a buck converter. 5. The method of claim 1 further comprising attaching an integrated circuit to said lead frame and electrically connecting said integrated circuit to said first and second transistors, said integrated circuit being encapsulated by said molding material to form a single module. 6. A method of making an integrated transistor module comprising: providing a planar lead frame having first and second spaced pads, one or more common source-drain leads located between said pads and one or more drain leads located on the outside of said second pad;flip chip attaching first and second transistors respectively to said first and second pads, each transistor having source, gate and drain electrodes, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads;attaching a first clip to the drain of said first transistor, said first clip having a planar member and a plurality of downwardly extending leads, and electrically connecting said first clip to said one or more common source-drain leads;attaching a second clip to the drain of said second transistor and electrically connecting said second clip to said one or more drain leads located on the outside of said second pad; andpartially encapsulating in molding material said lead frame, said transistors, and said clips with a portion of bottom surfaces of each of said first and second pads and said planar members of said clips being exposed to provide dual cooling of said module. 7. The method of claim 6 wherein the module further comprises leads extending outside the molding material. 8. The method of claim 6 wherein said first and second transistors are metal oxide semiconductor field effect transistors (MOSFET). 9. The method of claim 6 wherein said first and second transistors are respectively high side and low side power transistors that are components of a buck converter. 10. The method of claim 6 comprising the further steps of severing the lead frame between the first and second pads and attaching an electrical and thermal conductive third clip to the exposed portions of the first and second clips. 11. The method of claim 6 further comprising attaching an integrated circuit to said lead frame and electrically connecting said integrated circuit to said first and second transistors, said integrated circuit being encapsulated by said molding material to form a single module. 12. A method comprising: providing a planar lead frame having first and second spaced pads, one or more common source-drain leads located between said pads and one or more drain leads located on the outside of said second pad;flip chip attaching first and second transistors respectively to said first and second pads, each transistor having source, gate and drain electrodes, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads;attaching a first clip to the drain of said first transistor, said first clip having a planar member and a plurality of downwardly extending leads, and electrically connecting said first clip to said one or more common source-drain leads;attaching a second clip to the drain of said second transistor;partially encapsulating in molding material said lead frame, said transistors, and said clips with a portion of bottom surfaces of each of said first and second pads and said planar members of said clips being exposed to provide dual cooling of said module; andseparating the partially encapsulated first transistor is separated from the partially encapsulated second transistor to provide two separate transistors.
이 특허에 인용된 특허 (4)
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Butt Sheldon H. (Godfrey IL) Mahulikar Deepak (Meriden CT), Metal packages having improved thermal dissipation.
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Lin, Chang-Fu; Pu, Han-Ping; Hsiao, Cheng-Hsu; Huang, Chien Ping, Semiconductor package with heat sink attached to substrate.
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Kierse Oliver J.,IEX, Thermally efficient integrated circuit package.
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Yamunan, Vinu, Three-level leadframe for no-lead packages.
이 특허를 인용한 특허 (1)
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Pickering, William; Nielsen, Bruce A., Packaging a printed circuit board having a plurality of semiconductors in an inverter.
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