|국가/구분||United States(US) Patent 등록|
|국제특허분류(IPC7판)||G06F-015/173 G06F-009/46 G06F-003/00|
|미국특허분류(USC)||709/223; 718/102; 710/020|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 7 인용 특허 : 411|
A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value...
1. An integrated circuit comprising: a plurality of computing nodes;a memory in at least one of the plurality of computing nodes, the plurality of computing nodes configured to make memory requests for access to the memory;an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network providing interconnections among the plurality of computing nodes to route the memory requests;means for identifying a set of memory requests;means for determining when all of the memory requests in the set of memory requests...