PLD architecture for flexible placement of IP function blocks
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-017/50
G06F-007/38
출원번호
US-0465464
(2009-05-13)
등록번호
US-8201129
(2012-06-12)
발명자
/ 주소
Lee, Andy L.
McClintock, Cameron
Johnson, Brian
Cliff, Richard
Reddy, Srinivas
Lane, Chris
Leventis, Paul
Betz, Vaughn Timothy
Lewis, David
출원인 / 주소
Altera Corporation
대리인 / 주소
Ropes & Gray LLP
인용정보
피인용 횟수 :
3인용 특허 :
162
초록▼
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base si
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
대표청구항▼
1. A programmable logic device, comprising: a plurality of logic elements arranged in a predetermined pattern;a base signal routing architecture including a plurality of signal routing lines to route signals among the logic elements;at least one IP function block inserted into the predetermined patt
1. A programmable logic device, comprising: a plurality of logic elements arranged in a predetermined pattern;a base signal routing architecture including a plurality of signal routing lines to route signals among the logic elements;at least one IP function block inserted into the predetermined pattern in place of a two-dimensional portion of the logic elements, the insertion of the IP function block interrupting, at least in part, the base signal routing architecture; andan interface region existing between the logic elements and the IP function block, the interface region comprising interfacing circuitry operative to selectively apply signals to and from the IP function block. 2. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies a signal provided by the base signal routing architecture to the IP function block as a function block input signal. 3. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies a signal provided by a logic element immediately adjacent to the interface region to the IP function block as a function block input signal. 4. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies an IP function block output signal provided by the IP function block to the base signal routing architecture. 5. The programmable logic device of claim 1, wherein the interfacing circuitry selectively applies an IP function block output signal provided by the IP function block to a logic element immediately adjacent to the interface region. 6. The programmable logic device of claim 1, further comprising a plurality of memory blocks that are included within the predetermined pattern of logic elements, wherein the interface region exists between the memory blocks and the IP function block, the interface region comprising interfacing circuitry operative to route signals to and from the IP function block. 7. The programmable logic device of claim 6, wherein the interfacing circuitry selectively applies a signal provided by a memory block immediately adjacent to the interface region as a function block input signal. 8. The programmable logic device of claim 6, wherein the interfacing circuitry selectively applies an IP function block output signal provided by the IP function block to a memory block immediately adjacent to the interface region. 9. The programmable logic device of claim 1, wherein the interfacing circuitry comprises at least one multiplexer. 10. The programmable logic device of claim 1, wherein the interfacing circuitry comprises interfacing logic. 11. The programmable logic device of claim 1, further comprising a plurality of input/output pads, wherein the function block is incorporated into the predetermined pattern of logic elements such that the interfacing region has direct access to at least one of the input/output pads. 12. The programmable logic device of claim 1, further comprising a plurality of input/output pads, wherein the function block is incorporated into the predetermined pattern of logic elements such that it displaces at least one of the input/output pads. 13. The programmable logic device of claim 1, wherein the base signal routing architecture comprises short lines and long lines, wherein a first subset of the short lines connect to the IP function block and second subset of the short lines terminate at the IP function block while at least one long line is buffered over the IP function block. 14. The programmable logic device of claim 1, wherein the IP function block is selected from the group consisting of high-speed serial interface, a digital signal processor, a microprocessor, arithmetic logic unit, memory, random access memory, and a multiplier. 15. A semiconductor integrated circuit, comprising: a plurality of components arranged in a multi-dimensional array with at least one IP function block inserted into the array; anda base signal routing architecture connected to the components and at least partially interrupted by the IP function block, such that a first portion of the base routing architecture is coupled to the IP function block and a second portion of the base signal routing architecture is selectively applied over the IP function block. 16. The semiconductor integrated circuit of claim 15, wherein at least a subset of the first portion is terminated at the IP function block. 17. The programmable logic device of claim 16, wherein the IP function block is selected from the group consisting of high-speed serial interface, a digital signal processor, a microprocessor, arithmetic logic unit, memory, random access memory, and a multiplier. 18. The semiconductor integrated circuit of claim 15, wherein: the semiconductor integrated circuit further comprises an interface portion, whereinthe first portion of the base signal routing architecture is coupled to the IP function block via the interface portion. 19. The semiconductor integrated circuit of claim 15, wherein the base signal routing architecture includes long routing lines and short routing lines, wherein at least some of the long routing lines are routed across the IP function block and at least some of the short routing lines terminate or connect to the IP function block. 20. The semiconductor integrated circuit of claim 15, wherein the components comprise logic elements. 21. The semiconductor integrated circuit of claim 15, wherein the components comprise memory blocks. 22. The semiconductor integrated circuit of claim 15, wherein the multi-directional array is a three-dimensional array comprising rows and columns of the components that exist in layers in a plurality of layers. 23. The semiconductor integrated circuit of claim 22, wherein the first portion of the base signal routing architecture and the IP function block reside in a subplurality of the layers and wherein the second portion of the base signal routing architecture resides in layers other than the subplurality of layers. 24. The semiconductor integrated circuit of claim 15 wherein the IP function block is a first IP function block, the semiconductor integrated circuit further comprising: a second IP function block inserted into the multi-dimensional array of components, wherein the base signal routing architecture is at least partially interrupted by the second IP function block, such that a third portion of the base signal routing architecture is terminated at the second IP function block and a fourth portion of the base signal routing architecture is routed across the second IP function block. 25. The semiconductor integrated circuit of claim 15, wherein the timing of the second portion of the base signal routing architecture is delayed by less than a predetermined threshold as compared to the timing of a portion of the base signal routing architecture that is not interrupted by the IP function block and that spans approximately the same distance as the second portion. 26. A semiconductor integrated circuit, comprising: a plurality of components arranged in a multi-dimensional array with at least one IP function block inserted into the array; anda base signal routing architecture connected to the components and at least partially interrupted by the IP function block, such that a first portion of the base routing architecture is terminated at the IP function block and a second portion of the base signal routing architecture is selectively applied across the IP function block. 27. The semiconductor integrated circuit of claim 26, wherein: the semiconductor integrated circuit further comprises an interface portion, whereinsignals existing on the first portion of the base signal routing architecture are selectively routed to the IP function block via the interface portion. 28. The semiconductor integrated circuit of claim 26, wherein the components comprise logic elements. 29. The semiconductor integrated circuit of claim 26, wherein the components comprise memory elements. 30. The programmable logic device of claim 26, wherein the IP function block is selected from the group consisting of high-speed serial interface, a digital signal processor, a microprocessor, arithmetic logic unit, memory, random access memory, and a multiplier.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (162)
Sambamurthy Namakkal S. (San Jose CA) Lai Woo-Ping (San Jose CA) VanGilder John P. (Sunnyvale CA), Apparatus and method for full-duplex ethernet communications.
Sambamurthy Namakkal S. (San Jose CA) Lai Woo-Ping (San Jose CA) VanGilder John P. (Sunnyvale CA), Apparatus and method for full-duplex ethernet communications.
Muraoka Hiroshi (Kawasaki JPX) Fujisaku Kiminori (Sagamihara JPX), Apparatus for suspending the bus cycle of a microprocessor by inserting wait states.
Reddy Srinivas T. ; Zaveri Ketan ; Lane Christopher F. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B. ; Mejia Manuel ; Cliff Richard G., Circuitry and methods for internal interconnection of programmable logic devices.
Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.
Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
Hartmann Alfred C., Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip.
Tavana Danesh (Mountain View CA) Yee Wilson K. (Tracy CA) Holen Victor A. (Saratoga CA), FPGA architecture with repeatable tiles including routing matrices and logic matrices.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode.
Young Steven P. ; Bauer Trevor J. ; Chaudhary Kamal ; Krishnamurthy Sridhar, FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines.
Clifford Hessel ; Paul E. Voglewede ; Michael E. Kreeger ; Christopher D. Mackey ; Scott E. Marks ; Alfred W. Pietzold, III ; Louis M. Orsini ; John E. Gorton, Field programmable radio frequency communications equipment including a configurable if circuit, and method therefor.
Lien Jung-Cheun ; Huang Eddy Chieh ; Sun Chung-yuan ; Feng Sheng, Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template.
Ho Walford W. (Saratoga CA) Chen Chao-Chiang (Cupertino CA) Yang Yuk Y. (Foster City CA), Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array.
Pedersen Bruce B. (Santa Clara CA) Chiang David (Saratoga CA) Heile Francis B. (Santa Clara CA) McClintock Cameron (Mountain View CA) So Hock-Chuen (Redwood City CA) Watson James A. (Santa Clara CA), High-density erasable programmable logic device architecture using multiplexer interconnections.
Colwell Robert P. (Portland OR) Papworth David B. (Beaverton OR) Fetterman Michael A. (Hillsboro OR) Glew Andrew F. (Hillsboro OR) Hinton Glenn J. (Portland OR) Coward Stephen M. (Aloha OR) Chen Grac, Hybrid execution unit for complex microprocessor.
Andrews William B. ; Britton Barry K. ; Hickey Thomas J. ; Modo Ronald T. ; Nguyen Ho T. ; Schadt Lorraine L. ; Singh Satwant, Hybrid programmable gate arrays.
Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Lien Jung-Cheun ; Feng Sheng ; Sun Chung-yuan ; Huang Eddy Chieh, Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure.
Pierce Kerry M. (Canby OR) Erickson Charles R. (Fremont CA) Huang Chih-Tsung (Burlingame CA) Wieland Douglas P. (Sunnyvale CA), Interconnect architecture for field programmable gate array using variable length conductors.
Pierce Kerry M. ; Erickson Charles R. ; Huang Chih-Tsung ; Wieland Douglas P., Interconnect architecture for field programmable gate array using variable length conductors.
Yuan Chen-Ping ; Lin Che-Cheng ; Wei You-Pang, Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification.
Michihiro Amiya JP; Akihiro Nakamura JP, Library for storing pattern shape of connecting terminal and semiconductor circuit designed with different design rules.
Sutherland James (Santa Clara CA) Garverick Timothy L. (Cupertino CA) Takiar Hem P. (Fremont CA) Reyling ; Jr. George F. (Saratoga CA), Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module.
Rostoker Michael D. (Boulder Creek CA) Gluss David (Woodside CA) Harrington Tom (Mountain View CA), Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC.
Jose Maria Insenser Farre ES; Julio Faura Enriquez ES, Microprocessor based mixed signal field programmable integrated device and prototyping methodology.
Pass, Christopher J.; Sansbury, James D.; Madurawe, Raminda U.; Turner, John E.; Patel, Rakesh H.; Wright, Peter J., Nonvolatile memory cell with low doping region.
Ang, Roger; Ahuja, Atul; Lulla, Mukesh T.; Borkovic, Drazen; Small, Brian D.; Tralka, Charles C.; Chan, Andrew K.; Yee, Kevin K., Programmable device with an embedded portion for receiving a standard circuit design.
Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.
Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Pedersen Bruce B. (Santa Clara CA) Veenstra Kerry (San Jose CA), Programmable logic array having local and long distance conductors.
Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.
Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit devices with interleaved logic array blocks.
Cliff Richard G. (Milpitas CA) Cope L. Todd (San Jose CA) McClintock Cameron R. (Mountain View CA) Leong William (San Fransisco CA) Watson James A. (Santa Clara CA) Huang Joseph (San Jose CA) Ahanin , Programmable logic array integrated circuits.
Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA) Leong William (San Francisco CA), Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks.
Leong William (San Francisco CA) McClintock Cameron (Mountain View CA) Cliff Richard G. (Milpitas CA), Programmable logic array integrated circuits with interconnection conductors of overlapping extent.
Pedersen Bruce B. (Santa Clara CA) Cliff Richard G. (Santa Clara CA) Ahanin Bahram (Cupertino CA) Lytle Craig S. (Palo Alto CA) Heile Francis B. (Santa Clara CA) Veenstra Kerry S. (Concord CA), Programmable logic array with local and global conductors.
Wong Sau-Ching (Hillsborough CA) So Hock-Chuen (Milpitas CA) Kopec ; Jr. Stanley J. (San Jose CA) Hartmann Robert F. (San Jose CA), Programmable logic device with array blocks connected via programmable interconnect.
Reddy Srinivas T. ; Cliff Richard G. ; Lane Christopher F. ; Zaveri Ketan H. ; Mejia Manuel M. ; Jefferson David ; Pedersen Bruce B. ; Lee Andy L., Programmable logic device with hierarchical interconnection resources.
Reddy Srinivas T. ; Cliff Richard G. ; Lane Christopher F. ; Zaveri Ketan H. ; Mejia Manuel M. ; Jefferson David ; Pedersen Bruce B. ; Lee Andy L., Programmable logic device with hierarchical interconnection resources.
Reddy, Srinivas T.; Cliff, Richard G.; Lane, Christopher F.; Zaveri, Ketan H.; Mejia, Manuel M.; Jefferson, David; Pedersen, Bruce B.; Lee, Andy L., Programmable logic device with hierarchical interconnection resources.
Patel, Rakesh H.; Turner, John E., Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions.
Nguyen Bai ; Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Wong Jack T. ; Chang Herman M. ; Tran Giap H., Tileable and compact layout for super variable grain blocks within FPGA device.
Pressly Matthew D. ; Giles Grady L. ; Crouch Alfred L., Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation.
Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.