IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0433256
(2006-05-12)
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등록번호 |
US-8207760
(2012-06-26)
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발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
Blakely Sokoloff Taylor & Zafman LLP
|
인용정보 |
피인용 횟수 :
7 인용 특허 :
19 |
초록
▼
A method and an apparatus for implementing a semiconductor switch multi-stage drive circuit. The disclosed method and an apparatus reduce losses in a semiconductor switch when it is turned from an off state to an on state or from an on state to an off state. The reduction in losses is achieved witho
A method and an apparatus for implementing a semiconductor switch multi-stage drive circuit. The disclosed method and an apparatus reduce losses in a semiconductor switch when it is turned from an off state to an on state or from an on state to an off state. The reduction in losses is achieved without influencing the dv/dt across the semiconductor switch during a first time period while the semiconductor switch is switching. This reduction in losses is therefore achieved with very little increase in the noise generated due to rapid dv/dt during the first time period when the semiconductor switch is switching. The configuration of the circuitry to achieve this reduction in switching losses is such that benefits are less sensitive to manufacturing tolerances and temperature effects than alternative semiconductor switch drive schemes to achieve similar results.
대표청구항
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1. An apparatus, comprising: a semiconductor switch having a drive terminal, a first terminal and a second terminal, wherein the drive terminal is coupled to switch the semiconductor switch between on and off states;a first drive circuit coupled to provide a first drive signal to the drive terminal
1. An apparatus, comprising: a semiconductor switch having a drive terminal, a first terminal and a second terminal, wherein the drive terminal is coupled to switch the semiconductor switch between on and off states;a first drive circuit coupled to provide a first drive signal to the drive terminal of the semiconductor switch;a second drive circuit coupled to provide a second drive signal to the drive terminal of the semiconductor switch; anda selector circuit coupled to turn on the first and second drive circuits to provide the first and second drive signals, respectively, wherein a voltage at the drive terminal of the semiconductor switch temporarily clamps at a first voltage level during a time that the first drive circuit is providing the first drive signal and wherein the selector circuit turns on the second drive circuit after the voltage at the drive terminal unclamps and rises and responsive to a voltage between the first and second terminals of the semiconductor switch falling to a threshold value indicating a time at which the voltage at the drive terminal unclamps to a second voltage level, wherein the voltage between the first and second terminals has a fast changing time period transition and a subsequent slower changing time period transition, wherein the selector circuit turns on the second drive circuit after the fast changing time period transition is finished. 2. The apparatus of claim 1, wherein the second voltage level is greater than the first voltage level. 3. The apparatus of claim 1, wherein the selector circuit is coupled to the first terminal of the semiconductor switch to monitor the voltage between the first and second terminals. 4. The apparatus of claim 1, wherein the first terminal is a drain terminal of the semiconductor switch and wherein the second terminal is a source terminal of the semiconductor switch. 5. The apparatus of claim 1, further comprising a current sensor coupled between the semiconductor switch and the selector circuit. 6. The apparatus of claim 5, wherein the selector circuit turns on the second drive circuit in response to a current flow between the first terminal and the second terminal reaching a current threshold value indicating the unclamping of the drive terminal to the second voltage level. 7. The apparatus of claim 1, wherein the semiconductor switch is a metal oxide semiconductor field effect transistor (MOSFET). 8. The apparatus of claim 1, further comprising an impedance coupled between the drive terminal and the first and the second drive the circuits to provide impedance to both of the first and second drive circuits. 9. The apparatus of claim 8, wherein the impedance coupled between the drive terminal and the first and second drive circuits is a resistor. 10. The apparatus of claim 8, wherein a first end of the impedance is coupled to the drive terminal and wherein a second end of the impedance is coupled to the first drive circuit and the second drive circuit. 11. The apparatus of claim 10, wherein the second end of the impedance is not coupled to the first and second drive circuits through the impedance. 12. The apparatus of claim 1, wherein the first drive circuit includes a first MOSFET, coupled to provide the first drive signal to the drive terminal of the semiconductor switch, wherein the first MOSFET is driven to be fully enhanced when the first drive circuit is providing the first drive signal; andwherein the second drive circuit includes a second MOSFET, coupled to provide a second drive signal to the drive terminal of the semiconductor switch, wherein the second MOSFET is driven to be fully enhanced when the second drive circuit is providing the second drive signal. 13. An apparatus, comprising: a semiconductor switch having a drive terminal, a first terminal and a second terminal, wherein the drive terminal is coupled to switch the semiconductor switch between on and off states;a first drive circuit coupled to provide a first drive signal to the drive terminal of the semiconductor switch;a second drive circuit coupled to provide a second drive signal to the drive terminal of the semiconductor switch; anda selector circuit coupled to turn on the first and second drive circuits to provide the first and second drive signals, respectively, wherein a voltage at the drive terminal of the semiconductor switch temporarily clamps at a first voltage level during a time that the first drive circuit is providing the first drive signal and wherein the selector circuit turns on the second drive circuit after the voltage at the drive terminal unclamps and rises and responsive to a voltage between the first and second terminals of the semiconductor switch falling to a threshold value indicating a time at which the voltage at the drive terminal unclamps from the first voltage level, wherein the voltage between the first and second terminals has a fast changing time period transition and a subsequent slower changing time period transition, wherein the selector circuit turns on the second drive circuit after the fast changing time period transition is finished. 14. The apparatus of claim 13, wherein the drive terminal unclamps to a second voltage level, wherein the second voltage level is greater than the first voltage level. 15. The apparatus of claim 13, wherein the selector circuit is coupled to the first terminal of the semiconductor switch to monitor the voltage between the first and second terminals. 16. The apparatus of claim 13, wherein the first terminal is a drain terminal of the semiconductor switch and wherein the second terminal is a source terminal of the semiconductor switch. 17. The apparatus of claim 13, further comprising a current sensor coupled between the semiconductor switch and the selector circuit. 18. The apparatus of claim 17, wherein the selector circuit turns on the second drive circuit in response to a current flow between the first terminal and the second terminal reaching a current threshold value indicating the unclamping of the drive terminal from the first voltage level. 19. The apparatus of claim 13, wherein the semiconductor switch is a metal oxide semiconductor field effect transistor (MOSFET). 20. The apparatus of claim 13, wherein the first drive circuit includes a first MOSFET, coupled to provide the first drive signal to the drive terminal of the semiconductor switch, wherein the first MOSFET is driven to be fully enhanced when the first drive circuit is providing the first drive signal; andwherein the second drive circuit includes a second MOSFET, coupled to provide a second drive signal to the drive terminal of the semiconductor switch, wherein the second MOSFET is driven to be fully enhanced when the second drive circuit is providing the second drive signal.
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