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SIMD type microprocessor having processing elements that have plural determining units

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/76
출원번호 US-0167856 (2008-07-03)
등록번호 US-8219783 (2012-07-10)
우선권정보 JP-2007-175871 (2007-07-04)
발명자 / 주소
  • Hara, Kazuhiko
출원인 / 주소
  • Ricoh Company, Ltd.
대리인 / 주소
    Dickstein Shapiro LLP
인용정보 피인용 횟수 : 19  인용 특허 : 31

초록

An SIMD type microprocessor is disclosed. The SIMD type microprocessor includes plural PEs (processor elements) each of which provides an ALU (arithmetic and logic unit) for lower-order bits, an ALU for upper-order bits, a control circuit for lower-order bits, a control circuit for upper-order bits,

대표청구항

1. An SIMD (single instruction stream multiple data stream) type microprocessor, comprising: a processor element group including a plurality of processor elements each of which includes “n” (n is an integer of two or more) arithmetic circuits and an individual identifier unit; anda control unit whic

이 특허에 인용된 특허 (31)

  1. Radigan James J. (Sunnyvale CA) Schwartz David A. (Moorpark CA), Activity masking with mask context of SIMD processors.
  2. Matuda Motohiko (Amagasaki JPX) Yuasa Taiichi (Toyohashi JPX), Arithmetic unit for SIMD type parallel computer.
  3. Cotton John M. (East Norwalk CT), Associative processor with variable length fast multiply capability.
  4. Duluk ; Jr. Jerome F. (Santa Clara County CA), Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units.
  5. Hara Kazuhiko,JPX, Central processing unit.
  6. Hara Kazuhiko,JPX, Central processing unit adapted for pipeline process.
  7. Hara Kazuhiko,JPX ; Yamaura Shinichi,JPX ; Yoshioka Keiichi,JPX ; Nakamura Keiji,JPX ; Katayama Takao,JPX, Central processing unit compatible with bank register CPU.
  8. Hara Kazuhiko (Sanda JPX) Yamaura Shinichi (Kobe JPX) Yoshioka Keiichi (Sanda JPX) Katayama Takao (Ikeda JPX), Central processing unit including inhibited branch area.
  9. Hara Kazuhiko,JPX, Central processing unit with a selector that bypasses circuits where processing is not required.
  10. Kabemoto Akira,JPX ; Shibata Naohiro,JPX ; Muta Toshiyuki,JPX ; Shimamura Takayuki,JPX ; Sugahara Hirohide,JPX ; Nishioka Junji,JPX ; Sasaki Takatsugu,JPX ; Shinohara Satoshi,JPX ; Nakayama Yozo,JPX , Coherence apparatus for cache of multiprocessor.
  11. Hirai Takayasu,JPX ; Hara Kazuhiko,JPX, Data processor used in a data transfer system which includes a detection circuit for detecting whether processor uses bus in a forthcoming cycle.
  12. Abercrombie Andrew P. ; Duncan David A. ; Meeker Woodrow ; Schoomaker Ronald W. ; Van Dyke-Lewis Michele D., Directly accessing local memories of array processors for improved real-time corner turning processing.
  13. Yamaura Shinichi (Kobe JPX) Yoshioka Keiichi (Sanda JPX) Hara Kazuhiko (Ikeda JPX) Katayama Takao (Ikeda JPX), Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core.
  14. Wells David (Bolton MA) Tardiff James P. (Framingham MA) Satterfield David L. (Everett MA) Rowe Eric L. (Natick MA) Isman Marshall (Newton MA), Input/output system for parallel computer for performing parallel file transfers between selected number of input/output.
  15. Yamaura Shinichi (Takarazuka JPX) Hara Kazuhiko (Takatsuki JPX) Yoshioka Keiichi (Sanda JPX) Yasui Takashi (Toyonaka JPX), Integrated circuit comprising a central processing unit for executing a plurality of programs.
  16. Gallup Michael G. ; Goke L. Rodney ; Bell Meltin, Method and apparatus for performing a vector skip instruction in a data processor.
  17. Pechanek, Gerald George; Barry, Edwin Franklin; Stojancic, Mihailo M., Methods and apparatus for independent processor node operations in a SIMD array processor.
  18. Edwin F. Barry ; Gerald G. Pechanek ; Thomas L. Drabenstott ; Edward A. Wolff ; Nikos P. Pitsianis ; Grayson Morris, Methods and apparatus for manarray PE-PE switch control.
  19. Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.
  20. Katayama Takao,JPX ; Yamaura Shinichi,JPX ; Yoshioka Keiichi,JPX ; Hara Kazuhiko,JPX, Microprocessor having function of prefetching instruction.
  21. Kondo Yoshikazu (Hyogo JPX) Arima Yutaka (Hyogo JPX), Numerical arithmetic processing unit.
  22. Yamaura,Shinichi; Hara,Kazuhiko; Katayama,Takao; Iwanaga,Kazuhiko; Takafuji,Hiroshi, Parallel processor and image processing apparatus adapted for nonlinear processing through selection via processor element numbers.
  23. Ohki Mitsuharu,JPX, Parallel processor with memory/ALU inhibiting feature.
  24. McConnell, Ray, Processor memory system.
  25. Gschwind, Michael Karl; Hofstee, Harm Peter; Hopkins, Martin Edward, SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode.
  26. Inoue Yoshitsugu,JPX ; Kawai Hiroyuki,JPX ; Streitenberger Robert,JPX, SIMD processor operating with a plurality of parallel processing elements in synchronization.
  27. Shido Tatsuya (Kawasaki JPX) Kawamura Kaoru (Yokohama JPX) Umeda Masanobu (Yokohama JPX) Shibuya Toshiyuki (Inagi JPX) Miwatari Hideki (Yokohama JPX), SIMD system having logic units arranged in stages of tree structure and operation of stages controlled through respectiv.
  28. Gschwind,Michael Karl; Hofstee,Harm Peter; Hopkins,Martin E.; Kahle,James Allan, SIMD-RISC microprocessor architecture.
  29. Yamaura, Shin-ichi; Hara, Kazuhiko; Katayama, Takao; Iwanaga, Kazuhiko; Takafuji, Hiroshi, Single instruction stream multiple data stream processor.
  30. Yasui Takashi (Kobe JPX) Fukushima Masanobu (Toyonaka JPX) Hara Kazuhiko (Takatsuki JPX), System with selectively exclusionary enablement for plural indirect address type interrupt control circuit.
  31. Oberlin Steven M. ; Fromm Eric C. ; Passint Randal S., Virtual to logical to physical address translation for distributed memory massively parallel processing systems.

이 특허를 인용한 특허 (19)

  1. Chu, Sam G.; Kaltenbach, Markus; Le, Hung Q.; Leenstra, Jentje; Moreira, Jose E.; Nguyen, Dung Q.; Thompto, Brian W., Independent mapping of threads.
  2. Brownscheidle, Jeffrey Carl; Chadha, Sundeep; Delaney, Maureen Anne; Le, Hung Qui; Nguyen, Dung Quoc; Thompto, Brian William, Linkable issue queue parallel execution slice for a processor.
  3. Brownscheidle, Jeffrey Carl; Chadha, Sundeep; Delaney, Maureen Anne; Le, Hung Qui; Nguyen, Dung Quoc; Thompto, Brian William, Linkable issue queue parallel execution slice processing method.
  4. Eickemeyer, Richard J.; Hrusecky, David A.; McGlone, Elizabeth A.; Thompto, Brian W.; Van Norstrand, Jr., Albert J., Managing a divided load reorder queue.
  5. Smelyanskiy, Mikhail; Chen, Yen-Kuang; Kim, Daehyun; Hughes, Christopher J.; Lee, Victor W., Mechanism for conflict detection using SIMD.
  6. Hughes, Christopher J.; Ould-Ahmed-Vall, Elmoustapha; Valentine, Robert; Corbal, Jesus; Toll, Brett L.; Charney, Mark J.; Girkar, Milind B., Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality.
  7. Chadha, Sundeep; Cordes, Robert A.; Hrusecky, David A.; Le, Hung Q.; McGlone, Elizabeth A., Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions.
  8. Chadha, Sundeep; Cordes, Robert A.; Hrusecky, David A.; Le, Hung Q.; McGlone, Elizabeth A., Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions.
  9. Chadha, Sundeep; Cordes, Robert A.; Hrusecky, David A.; Le, Hung Q.; McGlone, Elizabeth A., Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions.
  10. Cordes, Robert A.; Hrusecky, David A.; Molnar, Jennifer L.; Paredes, Jose A.; Thompto, Brian W., Operation of a multi-slice processor implementing simultaneous two-target loads and stores.
  11. Cordes, Robert A.; Hrusecky, David A.; Molnar, Jennifer L.; Paredes, Jose A.; Thompto, Brian W., Operation of a multi-slice processor implementing simultaneous two-target loads and stores.
  12. Chadha, Sundeep; Hrusecky, David A.; McGlone, Elizabeth A.; Molnar, Jennifer L., Operation of a multi-slice processor preventing early dependent instruction wakeup.
  13. Fernsler, Kimberly M.; Hrusecky, David A.; Le, Hung Q.; McGlone, Elizabeth A.; Thompto, Brian W., Operation of a multi-slice processor with an expanded merge fetching queue.
  14. Ayub, Salma; Chadha, Sundeep; Cordes, Robert Allen; Hrusecky, David Allen; Le, Hung Qui; Nguyen, Dung Quoc; Thompto, Brian William, Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries.
  15. Eisen, Lee Evan; Le, Hung Qui; Leenstra, Jentje; Moreira, Jose Eduardo; Ronchetti, Bruce Joseph; Thompto, Brian William; Van Norstrand, Jr., Albert James, Processing of multiple instruction streams in a parallel slice processor.
  16. Eisen, Lee Evan; Le, Hung Qui; Leenstra, Jentje; Moreira, Jose Eduardo; Ronchetti, Bruce Joseph; Thompto, Brian William; Van Norstrand, Jr., Albert James, Reconfigurable parallel execution and load-store slice processor.
  17. Eisen, Lee Evan; Le, Hung Qui; Leenstra, Jentje; Moreira, Jose Eduardo; Ronchetti, Bruce Joseph; Thompto, Brian William; Van Norstrand, Jr., Albert James, Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices.
  18. Eisen, Lee Evan; Le, Hung Qui; Leenstra, Jentje; Moreira, Jose Eduardo; Ronchetti, Bruce Joseph; Thompto, Brian William; Van Norstrand, Jr., Albert James, Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices.
  19. Valentine, Robert; Charney, Mark J.; Corbal, Jesus; Girkar, Milind B.; Hughes, Christopher J.; Ould-Ahmed-Vall, Elmoustapha; Toll, Brett L., Vector address conflict resolution with vector population count functionality.
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