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Architecture and control of reed-solomon error-correction decoding 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03M-013/00
출원번호 US-0324285 (2008-11-26)
등록번호 US-8219894 (2012-07-10)
발명자 / 주소
  • Au, Siu-Hung Fred
  • Burd, Gregory
  • Wu, Zining
  • Xu, Jun
  • Kikuchi, Ichiro
  • Yoon, Tony
출원인 / 주소
  • Marvell International Ltd.
인용정보 피인용 횟수 : 27  인용 특허 : 18

초록

Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS

대표청구항

1. A method for decoding a dataword based on a decision-codeword using a Reed-Solomon decoder, the Reed-Solomon decoder comprising a first pipeline stage, a second pipeline stage, and a third pipeline stage, the method comprising: receiving a decision-codeword;producing a modified decision-codeword

이 특허에 인용된 특허 (18)

  1. Hassner,Martin Aureliano; Tamura,Tetsuya; Trager,Barry Marshall; Winograd,Shmuel, Algebraic decoder and method for correcting an arbitrary mixture of burst and random errors.
  2. Kauschke,Michael; Poppinga,Carsten, Apparatus for iterative hard-decision forward error correction decoding.
  3. Au,Siu Hung Fred; Burd,Gregory; Wu,Zining; Xu,Jun; Kikuchi,Ichiro; Yoon,Tony, Architecture and control of reed-solomon error-correction decoding.
  4. Au,Siu Hung Fred; Burd,Gregory; Wu,Zining; Xu,Jun; Kikuchi,Ichiro; Yoon,Tony, Architecture and control of reed-solomon list decoding.
  5. Burd, Gregory; Wu, Zining; Oberg, Mats; Sutardja, Pantas, Correcting errors in disk drive read back signals by iterating with the Reed-Solomon decoder.
  6. Fujita,Hachiro; Yoshida,Hideo, Decoding method and decoding apparatus of product code.
  7. Kato Masami,JPX, Digital transmission/receiving method, digital communications method, and data receiving apparatus.
  8. Kim, Min-Goo, Encoder/decoder with serial concatenated structure in communication system.
  9. Huang Wei-Hung,TWX, Error correction method and apparatus on optical disc system.
  10. Burd,Gregory, Iterative Reed-Solomon error-correction decoding.
  11. Lehobey,Fr챕d챕ric; Piret,Philippe, Low-cost methods and devices for the decoding of product cases.
  12. Joo Tae-shik (Seoul KRX) Lee Seok-jeong (Seoul KRX), Method for correcting multiple erroneous symbols in error correcting encoded data.
  13. Veksler Irina E. (Plantation FL), Method for decoding a reed solomon encoded signal with inner code and apparatus for doing same.
  14. Sako, Yoichiro; Odaka, Kentaro, Method for error correction.
  15. Arts Petrus (Eindhoven NLX), Method of and device for correcting errors and erasures in digital information.
  16. West Guy J. (Cedar Rapids IA), Periodic interference avoidance in a wireless radio frequency communication system.
  17. Kerr,Ron; Lodge,John; Guinand,Paul, Soft input decoding for linear codes.
  18. Wu,Zining; Burd,Gregory, Soft-output decoding method and apparatus for controlled intersymbol interference channels.

이 특허를 인용한 특허 (27)

  1. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W.; Jaser, Ihab, Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system.
  2. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W.; Jaser, Ihab, Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values.
  3. Norrie, Christopher I. W.; Marelli, Alessia; Micheloni, Rino; Onufryk, Peter Z., BCH data correction system and method.
  4. Marelli, Alessia; Micheloni, Rino, Background reference positioning and local reference positioning using threshold voltage shift read.
  5. Micheloni, Rino; Crippa, Luca; Marelli, Alessia, Error correction code technique for improving read stress endurance.
  6. Micheloni, Rino; Marelli, Alessia; Norrie, Christopher I. W., High quality log likelihood ratios determined using two-index look-up table.
  7. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W., Layer specific LDPC decoder.
  8. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W., Layer specific attenuation factor LDPC decoder.
  9. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab, Memory controller and integrated circuit device for correcting errors in data read from memory cells.
  10. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W., Method and apparatus for layer-specific LDPC decoding.
  11. Brown, David Alan; Onufryk, Peter Z.; Talledo, Cesar, Method and apparatus for translated routing in an interconnect switch.
  12. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Method and apparatus with program suspend using test mode.
  13. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend.
  14. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W., Nonvolatile memory controller with two-stage error correction technique for enhanced reliability.
  15. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory system with erase suspend circuit and method for erase suspend management.
  16. Micheloni, Rino, Nonvolatile memory system with program step manager and method for program step management.
  17. Micheloni, Rino; Marelli, Alessia; Bates, Stephen, Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction.
  18. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z., Shuffler error correction code system and method.
  19. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab; Crippa, Luca, System and method for accumulating soft information in LDPC decoding.
  20. Norrie, Christopher I. W., System and method for adaptive check node approximation in LDPC decoding.
  21. Norrie, Christopher I. W., System and method for avoiding error mechanisms in layered iterative decoding.
  22. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab; Crippa, Luca, System and method for higher quality log likelihood ratios in LDPC decoding.
  23. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W., System and method for lifetime specific LDPC decoding.
  24. Micheloni, Rino; Marelli, Alessia; Crippa, Luca, System and method for memory block pool wear leveling.
  25. Norrie, Christopher I. W., System and method for reduced memory storage in LDPC decoding.
  26. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z., System and method with reference voltage partitioning for low density parity check decoding.
  27. Graumann, Peter John Waldemar; Fard, Saeed Fouladi, Variable T BCH encoding.
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