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Structure for interconnect structure containing various capping materials for electrical fuse and other related applications 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
  • H01L-023/58
  • H01L-023/62
  • H01L-029/00
  • H01L-027/10
  • H01L-029/73
  • H01L-029/74
출원번호 US-0052662 (2011-03-21)
등록번호 US-8232649 (2012-07-31)
발명자 / 주소
  • Hsu, Louis L.
  • Tonti, William R.
  • Yang, Chih-Chao
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Canale, Anthony
인용정보 피인용 횟수 : 4  인용 특허 : 36

초록

A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first st

대표청구항

1. A structure comprising: a wiring interconnect structure having an interface comprising a metal wiring layer and a capping layer of a first material type; andan electronic fuse interconnect structure having an interface comprising a metal wiring layer and a capping layer of a second material type,

이 특허에 인용된 특허 (36)

  1. Yang, Chih-Chao; Clevenger, Lawrence A.; Dalton, Timothy J.; Fuller, Nicholas C.; Hsu, Louis C., Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application.
  2. Yang,Chih Chao; Clevenger,Lawrence A.; Dalton,Timothy J.; Fuller,Nicholas C.; Hsu,Louis C., Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application.
  3. Anderson,Brent A.; Bryant,Andres; Gambino,Jeffrey P.; Stamper,Anthony K., Air-gap insulated interconnections.
  4. Dubin, Valery M.; Moon, Peter K., Apparatus for an improved air gap interconnect structure.
  5. Adkisson, James W.; Gambino, Jeffrey P.; Jaffe, Mark D.; Rassel, Richard J., Bond pad for wafer and package for CMOS imager.
  6. Sudijono, John; Hsia, Liang Ch O; Ping, Liu Wu, Copper recess formation using chemical process for fabricating barrier cap for lines and vias.
  7. Ngo, Minh Van; Besser, Paul Raymond; Zhao, Larry, Cu capping layer deposition with improved integrated circuit reliability.
  8. Wang, Ping-Chuan; Li, Wai-Kin, Empty vias for electromigration during electronic-fuse re-programming.
  9. Barth, Hans-Joachim; Felsner, Petra; Kaltalioglu, Erdem; Friese, Gerald, FBEOL process for Cu metallizations free from Al-wirebond pads.
  10. Yu, Ta-Lee, Fabricating an electrical metal fuse.
  11. Sakoh,Takashi, Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance.
  12. Ngo Minh Van ; Cheung Robin W., High density capping layers with improved adhesion to copper interconnects.
  13. Yang,Chih Chao, High-density 3-dimensional resistors.
  14. Oda Noriaki,JPX, Method for fabricating multilevel interconnection structure for semiconductor devices.
  15. van Ngo, Minh, Method for forming nitride capped Cu lines with reduced hillock formation.
  16. Wong,Lawrence D.; Leu,Jihperng; Kloster,Grant; Ott,Andrew; Morrow,Patrick, Method of making semiconductor device using a novel interconnect cladding layer.
  17. Leu, Jihperng; Thomas, Christopher D., Method of making semiconductor device using an interconnect.
  18. Takewaki, Toshiyuki; Kunishima, Hiroyuki, Narrow and wide copper interconnections composed of (111), (200) and (511) surfaces.
  19. Wang, Ming-Tsong; Ong, Tong-Chern, One-time-programmable anti-fuse formed using damascene process.
  20. Tzeng Wen-Tsing,TWX ; Yang Chun-Pin,TWX ; Lin Hsing-Lien,TWX, Passivation layer etching process for memory arrays with fusible links.
  21. Yang,Chao Hsiang, Protective metal structure and method to protect low-K dielectric layer during fuse blow process.
  22. Chao-Kun Hu ; Robert Rosenberg ; Judith Marie Rubino ; Carlos Juan Sambucetti ; Anthony Kendall Stamper, Reduced electromigration and stressed induced migration of Cu wires by surface coating.
  23. Joshi Rajiv V. (Yorktown Heights NY) Cuomo Jerome J. (Lincolndale NY) Dalal Hormazdyar M. (Milton NY) Hsu Louis L. (Fishkill NY), Refractory metal capped low resistivity metal conductor lines and vias.
  24. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
  25. Burke, Peter A.; Hose, Sallie; Shastri, Sudhama C., Semiconductor component and method of manufacture.
  26. Noguchi,Junji; Matsumoto,Takashi; Oshima,Takayuki; Onozuka,Toshihiko, Semiconductor device and manufacturing method of the same.
  27. Takeda,Kenichi; Ryuzaki,Daisuke; Hinode,Kenji; Mine,Toshiyuki, Semiconductor device and method manufacturing the same.
  28. Park, Seung Han; Lee, Ki Young, Semiconductor device having fuse and capacitor at the same level and method of fabricating the same.
  29. Park,Seung Han; Lee,Ki Young, Semiconductor device having fuse and capacitor at the same level and method of fabricating the same.
  30. Harada,Takeshi, Semiconductor device having via connecting between interconnects.
  31. Hotta, Katsuhiko; Sasahara, Kyoko; Hayamizu, Taichi; Kawano, Yuichi, Semiconductor device with fuse and a method of manufacturing the same.
  32. Makoto Kotou JP; Shinya Iwasa JP, Semiconductor memory device manufacturing method with fuse cutting performance improved.
  33. Yang, Chih Chao; Edelstein, Daniel C.; Mandelman, Jack A.; Hsu, Louis L., Semiconductor structure for fuse and anti-fuse applications.
  34. Yang, Chih-Chao; Hsu, Louis C.; Joshi, Rajiv V., Simultaneous grain modulation for BEOL applications.
  35. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  36. Duesman, Kevin G.; Farnworth, Warren M., Utilization of die active surfaces for laterally extending die internal and external connections.

이 특허를 인용한 특허 (4)

  1. Basker, Veeraraghavan S.; Cheng, Kangguo; Khakifirooz, Ali; Li, Juntao, Electrical fuse and/or resistor structures.
  2. Basker, Veeraraghavan S.; Cheng, Kangguo; Khakifirooz, Ali; Li, Juntao, Electrical fuse and/or resistor structures.
  3. Basker, Veeraraghavan S.; Cheng, Kangguo; Khakifirooz, Ali; Li, Juntao, Electrical fuse and/or resistor structures.
  4. Basker, Veeraraghavan S.; Cheng, Kangguo; Khakifirooz, Ali; Li, Juntao, Electrical fuse and/or resistor structures.
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