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Integrated circuit mounted board, printed wiring board, and method of manufacturing integrated circuit mounted board

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/16
출원번호 US-0702616 (2010-02-09)
등록번호 US-8247702 (2012-08-21)
우선권정보 JP-2009-46631 (2009-02-27)
발명자 / 주소
  • Kouya, Takuya
출원인 / 주소
  • Denso Corporation
대리인 / 주소
    Posz Law Group, PLC
인용정보 피인용 횟수 : 34  인용 특허 : 6

초록

An integrated circuit mounted board includes a printed wiring board and an integrated circuit bare chip mounted on the printed wiring board. The printed wiring board includes a metal base, an insulating member made of an insulating material and disposed on the metal base, and a wiring pattern dispos

대표청구항

1. An integrated circuit mounted board comprising a printed wiring board and an integrated circuit bare chip mounted on the printed wiring board, wherein: the printed wiring board includes a metal base, an insulating member made of an insulating material and disposed on the metal base, and a wiring

이 특허에 인용된 특허 (6)

  1. Rosenau Bernhard (Neustadt DEX) Hisgen Bernd (Limburgerhof DEX) Heinz Gerhard (Weisenheim DEX) Braun Hans-Georg (Gruenstadt DEX) Lausberg Dietrich (Ludwigshafen DEX) Zeiner Hartmut (Ludwigshafen DEX), Blends of thermotropic polymers with polyesters and polycarbonate.
  2. Ono, Atsushi; Asazu, Takuro; Yamaguchi, Shinji, Method for manufacturing a semiconductor device.
  3. Mok Sammy L., Multiple chip module assembly for top of mother board.
  4. Wakabayashi, Yoshiaki; Tohya, Hirokazu; Yamaguchi, Kouichi; Higuchi, Akiji; Yamada, Kenji, Nanoparticle transmission line element and method of fabricating the same.
  5. Tsuji Kazuto,JPX ; Yoneda Yoshiyuki,JPX ; Sakoda Hideharu,JPX ; Nomoto Ryuuji,JPX ; Watanabe Eiji,JPX ; Orimo Seiichi,JPX ; Onodera Masanori,JPX ; Kasai Junichi,JPX, Semiconductor device including a frame terminal.
  6. Materna Peter (Metuchen NJ) Mahon Geoffrey L. (Ridgewood NJ), Temperature compensated stored gas inflator.

이 특허를 인용한 특허 (34)

  1. Rathburn, James, Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection.
  2. Rathburn, James, Bumped semiconductor wafer or die level electrical interconnect.
  3. Rathburn, James, Compliant printed circuit area array semiconductor device package.
  4. Rathburn, James, Compliant printed circuit semiconductor package.
  5. Rathburn, James, Compliant printed circuit semiconductor tester interface.
  6. Rathburn, James, Compliant printed circuit wafer level semiconductor package.
  7. Rathburn, James, Compliant printed flexible circuit.
  8. Rathburn, James, Composite polymer-metal electrical contacts.
  9. Rathburn, Jim, Copper pillar full metal via electrical circuit structure.
  10. Rathburn, James, Direct metalization of electrical circuit structures.
  11. Rathburn, James, Electrical connector insulator housing.
  12. Rathburn, James, Electrical interconnect IC device socket.
  13. Rathburn, James, Electrical interconnect IC device socket.
  14. Rathburn, James, Fusion bonded liquid crystal polymer circuit structure.
  15. Rathburn, James, High performance electrical circuit structure.
  16. Rathburn, James, High performance surface mount electrical interconnect.
  17. Rathburn, James, High performance surface mount electrical interconnect.
  18. Rathburn, James, High performance surface mount electrical interconnect.
  19. Rathburn, James, High performance surface mount electrical interconnect with external biased normal force loading.
  20. Rathburn, James, High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly.
  21. Rathburn, James, Hybrid printed circuit assembly with low density main core and embedded high density circuit regions.
  22. Rathburn, James J., Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction.
  23. Rathburn, James J., Mechanical contact retention within an electrical connector.
  24. Rathburn, James, Metalized pad to electrical contact interface.
  25. Rathburn, James, Method of forming a semiconductor socket.
  26. Rathburn, James J., Method of making an electrical connector having electrodeposited terminals.
  27. Rathburn, Jim, Method of making an electronic interconnect.
  28. Rathburn, James, Performance enhanced semiconductor socket.
  29. Rathburn, James, Resilient conductive electrical interconnect.
  30. Rathburn, Jim, Selective metalization of electrical connector or socket housing.
  31. Rathburn, James, Semiconductor device package adapter.
  32. Rathburn, James, Semiconductor die terminal.
  33. Rathburn, James, Semiconductor socket with direct selective metalization.
  34. Rathburn, James, Singulated semiconductor device separable electrical interconnect.
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