초록 ▼

An apparatus and a method switch a load through a power transistor. The apparatus includes: a first current generator for generating a current to charge a capacitance of a control terminal of the power transistor during power on of the power transistor; a second current generator for generating a cu

An apparatus and a method switch a load through a power transistor. The apparatus includes: a first current generator for generating a current to charge a capacitance of a control terminal of the power transistor during power on of the power transistor; a second current generator for generating a current to discharge the capacitance during power off of the power transistor. The apparatus is equipped with control circuitry having a storage element for storing a voltage value representative of the potential difference between the control terminal and a conduction terminal of the power transistor when the power transistor operates in the saturation region and a discharge circuit for generating an additional current to discharge the capacitance during the power-off process. The additional current is a function of the potential difference of the control terminal and the stored voltage value from the conduction terminal.

대표청구항 ▼

1. A driver circuit for switching a load through a power transistor comprising: a first current generator configured to be controlled by a first signal and structured to charge a capacitance of a control terminal of said power transistor during power on of said power transistor by generating a charg

1. A driver circuit for switching a load through a power transistor comprising: a first current generator configured to be controlled by a first signal and structured to charge a capacitance of a control terminal of said power transistor during power on of said power transistor by generating a charge current;a second current generator configured to be controlled by a second signal, said second generator being structured to discharge said capacitance of said control terminal of said power transistor during power off of said power transistor by generating a first discharge current;a control circuit electrically coupled to said second current generator and configured to be coupled to said control terminal of said power transistor, said control circuit comprising: a storage element structured to store a voltage value, which is representative of a potential difference between said control terminal and a conduction terminal of said power transistor when said power transistor operates in a saturation region, anda discharge circuit structured to discharge said capacitance of said control terminal of said power transistor during said power off process by generating a second discharge current, said second discharge current being a function of said stored voltage value, wherein the storage element is part of a sample and hold circuit configured to sample the potential difference between said drive terminal and a conduction terminal of said power transistor when said power transistor operates in the saturation region. 2. A driver circuit as claimed in claim 1, wherein: said storage element includes a capacitance positioned between an intermediate node and a ground terminal;the control circuit further includes a voltage differentiator structured to detect said voltage value; andthe sample and hold circuit includes a first switch positioned between the intermediate node and the control terminal of the power transistor and configured to sample said voltage value into the capacitance of the storage element. 3. A driver circuit as claimed in claim 2, wherein said control circuit further comprises: a third current generator;a second switch coupled to the third current generator; anda logical control block configured to, in response to detecting that a voltage in said capacitance of said storage element is zero, control said second switch into enabling the third current generator to charge said capacitance to a voltage equal to or higher than a threshold voltage of said power transistor. 4. A driver circuit as claimed in claim 2, wherein said first switch has a control terminal coupled to the voltage differentiator, the first switch being configured to sample the voltage value into the capacitance in response to the voltage differentiator detecting the voltage value. 5. A driver circuit as claimed in claim 1, wherein said discharge circuit includes: a third current generator structured to generate the additional current; anda differential amplifier having a first input configured to receive said voltage value, a second input configured to receive a value representative of a voltage of said control terminal of said power transistor, and an output, the differential amplifier being structured to generate at its output a control signal for actuating the third generator to deliver said second discharge current as long as said control signal is nonzero. 6. A driver circuit as claimed in claim 5, wherein said storage element includes a capacitance, the sample and hold circuit is configured to sample said voltage value into the capacitance, and the control circuit further includes a voltage differentiator structured to detect said voltage value, the driver circuit further comprising: first and second switches coupled to said first and second current generators, respectively;a logical control block coupled to said control circuitry and said first and second switches, said logical control block being configured to receive a first enabling signal for enabling said power transistor and a second enabling signal for enabling said logical control block to control operation of said control circuitry, said logical control block being configured to control:said first and second current generators via first and second control signals controlling the first and second switches respectively,said differential amplifier by a third control signal, andsaid sample and hold circuit by a fourth control signal, which in turn depends on a fifth control signal from said voltage differentiator. 7. A driver circuit as claimed in claim 1, wherein said control circuit comprises an overdrive block configured to receive said voltage value and provide an overdrive voltage to said control terminal of said power transistor. 8. A driving method, comprising: switching a load through a power transistor having a control terminal;generating a first discharging current;detecting a time at which a voltage between said control terminal and a conduction terminal of said power transistor is such that the power transistor operates in the saturation region;sampling said voltage into a storage element;generating a second discharging current proportional to a difference between said sampled voltage and a voltage of said control terminal;discharging the control terminal using the first and second discharging currents; andstopping said second discharging current in response to detecting that said difference becomes zero. 9. A driving method as claimed in claim 8, comprising: detecting that said storage element has a voltage of zero;in response to detecting that the voltage in said storage element is zero, generating a charging current for charging said capacitance to a selected voltage equal to or higher than a threshold voltage of said power transistor; andstopping said charging current in response to detecting that said selected voltage has been reached. 10. A driving method as claimed in claim 8, comprising powering on said power transistor by providing a voltage to the control terminal, which is equal to a sum of said selected voltage and an overdrive voltage. 11. A power circuit for driving a load, comprising: a power transistor configured to be coupled to the load, the power transistor including a parasitic capacitance; anda drive circuit coupled to the power transistor and configured to drive the power transistor, the drive circuit including: a first current generator configured to be controlled by a first signal and structured to charge the parasitic capacitance of a control terminal of said power transistor during power on of said power transistor by generating a charge current;a second current generator controlled by a second signal, said second generator being structured to discharge said parasitic capacitance of said control terminal of said power transistor during power off of said power transistor by generating a first discharge current; anda control circuit electrically coupled to said second current generator and to said control terminal of said power transistor, said control circuit comprising: a storage element structured to store a voltage value, which is representative of a potential difference between said drive terminal and a conduction terminal of said power transistor when said power transistor operates in a saturation region, wherein said storage element includes a capacitance positioned between an intermediate node and a ground terminal;a discharge circuit structured to discharge said capacitance of said control terminal of said power transistor during said power off process by generating a second discharge current, said second discharge current being a function of said stored voltage value;a voltage differentiator structured to detect said voltage value; anda first switch positioned between the intermediate node and the control terminal of the power transistor and configured to sample said voltage value into the capacitance of the storage element. 12. A power circuit as claimed in claim 11, wherein said control circuit further comprises: a third current generator;a second switch coupled to the third current generator; anda logical control block configured to, in response to detecting that a voltage in said capacitance is zero, control said second switch into enabling the third current generator to charge said capacitance to a voltage equal to or higher than a threshold voltage of said power transistor. 13. A power circuit as claimed in claim 11, wherein said first switch has a control terminal coupled to the voltage differentiator, the first switch being configured to sample the voltage value into the capacitance in response to the voltage differentiator detecting the voltage value. 14. A power circuit as claimed in claim 11, wherein said discharge circuit includes: a third current generator structured to generate the additional current; anda differential amplifier having a first input configured to receive said voltage value, a second input configured to receive a value representative of a voltage of said control terminal of said power transistor, and an output, the differential amplifier being structured to generate at its output a control signal for actuating the third generator to deliver said second discharge current as long as said control signal is nonzero. 15. A power circuit as claimed in claim 14, wherein the control circuit further includes a voltage differentiator structured to detect said voltage value, the driver circuit further comprising: second and third switches coupled to said first and second current generators, respectively;a logical control block coupled to said control circuitry and said second and third switches, said logical control block being configured to receive a first enabling signal for enabling said power transistor and a second enabling signal for enabling said logical control block to control operation of said control circuitry, said logical control block being configured to control:said first and second current generators via first and second control signals controlling the first and second respectively,said differential amplifier by a third control signal, andsaid first switch by a fourth control signal, which in turn depends on a fifth control signal from said voltage differentiator. 16. A power circuit as claimed in claim 11, wherein said control circuit comprises an overdrive block configured to receive said voltage value and provide an overdrive voltage to said control terminal of said power transistor. 17. A power circuit as claimed in claim 11, wherein said control terminal of the transistor is a gate and the conduction terminal is a source. 18. A driver circuit for controlling a power transistor comprising: a first current generator configured to charge a capacitance of a control terminal of said power transistor during power on of said power transistor by generating a charge current;a second current generator configured to discharge said capacitance of said control terminal of said power transistor by generating a first discharge current through a first discharge current path during power off of said power transistor;a control circuit configured to be coupled to said control terminal of said power transistor, said control circuit including:a storage element configured to store a Miller voltage of said power transistor; anda detector circuit configured to detect that the power transistor has reached a Miller zone during the power off of said power transistor;a fast discharge circuit structured to compare a voltage of the control terminal of the power transistor with the Miller voltage stored in the storage element, discharge the capacitance of said control terminal of said power transistor by generating a second discharge current through a second discharge current path, and stop the second discharge current in response to the detector circuit detecting that the power transistor has reached the Miller zone. 19. A driver circuit as claimed in claim 18, wherein the control circuit includes an overdrive circuit structured to drive the power transistor in triode region by providing to the gate of the power transistor a voltage that is a sum of the Miller voltage stored in the storage element and a fixed overdrive voltage. 20. A driver circuit as claimed in claim 18, wherein said storage element includes a capacitance and said control circuit further comprises: a third current generator configured to provide a second charge current;a switch coupled to the third current generator; anda logical control block configured to, in response to detecting that a voltage in said capacitance of the storage element is zero, control said switch into enabling the third current generator to charge said capacitance of the storage element to a voltage equal to or higher than a threshold voltage of said power transistor. 21. A driver circuit as claimed in claim 18, wherein said control circuit further comprises a switch having a control terminal coupled to the detector circuit, the switch being configured to sample a voltage of the control terminal into the capacitance of the storage element in response to the detection circuit detecting that the power transistor has reached the Miller zone during the power off of said power transistor. 22. A driver circuit as claimed in claim 18, further comprising: an output node configured to be coupled to the control terminal of the power transistor; anda ground terminal, wherein:the first current path extends between the output node and the ground terminal and includes the second current generator and a switch;the second current path extends between the output node and the ground terminal and includes a third current generator of the fast discharge circuit; andthe control circuit includes a control logic block configured to control the switch and the fast discharge circuit and cause the second and third current generators to simultaneously provide the first and second discharge currents from the output node to the ground terminal. 23. A driver circuit for switching a load through a power transistor comprising: a first current generator configured to be controlled by a first signal and structured to charge a capacitance of a control terminal of said power transistor during power on of said power transistor by generating a charge current;a second current generator configured to be controlled by a second signal, said second generator being structured to discharge said capacitance of said control terminal of said power transistor during power off of said power transistor by generating a first discharge current;a control circuit electrically coupled to said second current generator and configured to be coupled to said control terminal of said power transistor, said control circuit comprising: a storage element structured to store a voltage value, which is representative of a potential difference between said control terminal and a conduction terminal of said power transistor when said power transistor operates in a saturation region, wherein said storage element includes a capacitance positioned between an intermediate node and a ground terminal;a discharge circuit structured to discharge said capacitance of said control terminal of said power transistor during said power off process by generating a second discharge current, said second discharge current being a function of said stored voltage value;a voltage differentiator structured to detect said voltage value; anda switch positioned between the intermediate node and the control terminal of the power transistor and configured to sample said voltage value into the capacitance of the storage element. 24. A driver circuit as claimed in claim 23, wherein said control circuit further comprises: a third current generator;a switch coupled to the third current generator; anda logical control block configured to, in response to detecting that a voltage in said capacitance of said storage element is zero, control said switch into enabling the third current generator to charge said capacitance to a voltage equal to or higher than a threshold voltage of said power transistor. 25. A driver circuit as claimed in claim 23, wherein said first switch has a control terminal coupled to the voltage differentiator, the first switch being configured to sample the voltage value into the capacitance in response to the voltage differentiator detecting the voltage value. 26. A driver circuit for switching a load through a power transistor comprising: a first current generator configured to be controlled by a first signal and structured to charge a capacitance of a control terminal of said power transistor during power on of said power transistor by generating a charge current;a second current generator configured to be controlled by a second signal, said second generator being structured to discharge said capacitance of said control terminal of said power transistor during power off of said power transistor by generating a first discharge current;a control circuit electrically coupled to said second current generator and configured to be coupled to said control terminal of said power transistor, said control circuit comprising: a storage element structured to store a voltage value, which is representative of a potential difference between said control terminal and a conduction terminal of said power transistor when said power transistor operates in a saturation region;a discharge circuit structured to discharge said capacitance of said control terminal of said power transistor during said power off process by generating a second discharge current, said second discharge current being a function of said stored voltage value; andan overdrive block configured to receive said voltage value and provide an overdrive voltage to said control terminal of said power transistor. 27. A driver circuit as claimed in claim 26, wherein said storage element includes a capacitance positioned between an intermediate node and a ground terminal, the control circuit further comprising: a voltage differentiator structured to detect said voltage value; anda switch positioned between the intermediate node and the control terminal of the power transistor and configured to sample said voltage value into the capacitance of the storage element. 28. A power circuit for driving a load, comprising: a power transistor configured to be coupled to the load, the power transistor including a parasitic capacitance; anda drive circuit coupled to the power transistor and configured to drive the power transistor, the drive circuit including: a first current generator configured to be controlled by a first signal and structured to charge the parasitic capacitance of a control terminal of said power transistor during power on of said power transistor by generating a charge current;a second current generator controlled by a second signal, said second generator being structured to discharge said parasitic capacitance of said control terminal of said power transistor during power off of said power transistor by generating a first discharge current; anda control circuit electrically coupled to said second current generator and to said control terminal of said power transistor, said control circuit comprising: a storage element structured to store a voltage value, which is representative of a potential difference between said drive terminal and a conduction terminal of said power transistor when said power transistor operates in a saturation region, anda discharge circuit structured to discharge said capacitance of said control terminal of said power transistor during said power off process by generating a second discharge current, said second discharge current being a function of said stored voltage value, wherein the storage element is part of a sample and hold circuit configured to sample the potential difference between said drive terminal and a conduction terminal of said power transistor when said power transistor operates in the saturation region. 29. A power circuit as claimed in claim 28, wherein: said storage element includes a capacitance positioned between an intermediate node and a ground terminal;the control circuit further includes a voltage differentiator structured to detect said voltage value; andthe sample and hold circuit includes a first switch positioned between the intermediate node and the control terminal of the power transistor and configured to sample said voltage value into the capacitance of the storage element. 30. A power circuit as claimed in claim 29, wherein said control circuit further comprises: a third current generator;a second switch coupled to the third current generator; anda logical control block configured to, in response to detecting that a voltage in said capacitance of said storage element is zero, control said second switch into enabling the third current generator to charge said capacitance to a voltage equal to or higher than a threshold voltage of said power transistor. 31. A power circuit as claimed in claim 29, wherein said first switch has a control terminal coupled to the voltage differentiator, the first switch being configured to sample the voltage value into the capacitance in response to the voltage differentiator detecting the voltage value.