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Metal interconnect structure with a side wall spacer that protects an ARC layer and a bond pad from corrosion and method of forming the metal interconnect structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C23F-001/00
  • B44C-001/22
  • H01B-013/00
  • H01B-005/00
출원번호 US-0714450 (2010-02-27)
등록번호 US-8282846 (2012-10-09)
발명자 / 주소
  • Hill, Rodney L.
출원인 / 주소
  • National Semiconductor Corporation
대리인 / 주소
    Conser, Eugene C.
인용정보 피인용 횟수 : 2  인용 특허 : 21

초록

A metal interconnect structure, which includes a bond pad, an overlying anti-reflective coating layer, an overlying passivation layer, and an opening that exposes a top surface of the bond pad, eliminates corrosion resulting from the anti-reflective layer being exposed to moisture during reliability

대표청구항

1. A method for preventing metal corrosion on a bond pad of an integrated circuit device, the method comprising the steps of: applying an anti-reflective coating layer to the bond pad; depositing a passivation layer over the anti-reflective coating layer and etching an aperture through the passivati

이 특허에 인용된 특허 (21)

  1. Mei Sheng Zhou SG; Sangki Hong SG; Simon Chooi SG, Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects.
  2. Friese, Gerald; Robl, Werner K.; Barth, Hans-Joachim; Brintzinger, Axel, Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level.
  3. Leung Pak K. (Kanata CAX) Emesh Ismail T. (Cumberland CAX), Capacitor for an integrated circuit and method of formation thereof, and a method of adding on-chip capacitors to an int.
  4. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.
  5. Cooney, III, Edward C; Geffken, Robert M; Stamper, Anthony K, Metal spacer in single and dual damascene processing.
  6. Ding Ji ; Shan Hongching ; Welch Michael, Method for etching dielectric using fluorohydrocarbon gas, NH.sub.3 -generating gas, and carbon-oxygen gas.
  7. Bowen, Carl L.; Lao, Keith Q., Method for forming an integrated circuit having a bonding pad and a fuse.
  8. Yoshizumi Keiichi (Kokubunji JPX) Fukuda Kazushi (Kodaira JPX) Ariga Seiichi (Ohme JPX) Ikeda Shuji (Koganei JPX) Saeki Makoto (Ohme JPX) Nagai Kiyoshi (Kodaira JPX) Hashiba Soichiro (Nagoya JPX) Nis, Method for manufacturing semiconductor integrated circuit device having a fuse element.
  9. Gabriel Calvin T. (Pacifica CA), Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges.
  10. Lee Chung-Kuang,TWX ; Tseng Pin-Nan,TWX, Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnec.
  11. Chang Kenneth (Hopewell Junction NY) Czornyj George (Poughkeepsie NY) Farooq Mukta S. (Hopewell Junction NY) Kumar Ananda H. (Hopewell Junction NY) Pitler Marvin S. (late of Poughkeepsie NY by Peter , Method of making a multilayer thin film structure.
  12. Alain Blosse ; Sanjay Thedki ; Jianmin Qiao ; Yitzhak Gilboa, Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer.
  13. Obeng Yaw Samuel ; Obeng Jennifer S., Passivated copper surfaces.
  14. Efland Taylor R. ; Skelton Dale J. ; Mai Quang X. ; Williams Charles E., Plastic encapsulation for integrated circuits having plated copper top surface level interconnect.
  15. Cote William J. (Essex Junction VT) Kenney Donald M. (Shelburne VT) Kerbaugh Michael L. (Burlington VT) Leach Michael A. (Winooski VT) Robinson Jeffrey A. (Essex Junction VT) Sweetser Robert W. (Esse, Process for defining organic sidewall structures.
  16. Yang, Gwo-Shii; Chen, Jen Kon; Chen, Hsueh-Chung; Barth, Hans-Joachim; Hsiung, Chiung-Sheng; Liu, Chih-Chien; Chen, Tong-Yu; Lin, Yi-hsiung; Yang, Chih-Chao, Process for forming fusible links.
  17. Chung W Ho ; Tsing-Chow Wang, Process to make a tall solder ball by placing a eutectic solder ball on top of a high lead solder ball.
  18. Su, Yea-Zan; Huang, Cheng-Chung; Hsu, Huai-Jen; Chang, Wen-Tsan, Reinforced aluminum copper bonding pad.
  19. Abercrombie David A. ; Brownson Rickey S. ; Cherniawski Michael R., Semiconductor component with multi-level interconnect system and method of manufacture.
  20. Fujisawa, Kazunori; Awaya, Nobuyoshi, Semiconductor device and its production process.
  21. Strobl Peter, Semiconductor manufacturing method.

이 특허를 인용한 특허 (2)

  1. Lake, Rickie C., Methods for forming conductive elements and vias on substrates.
  2. Lake, Rickie C., Methods for forming conductive elements and vias on substrates and for forming multi-chip modules.
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