Preserving stopband characteristics of electromagnetic bandgap structures in circuit boards
IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0244854
(2008-10-03)
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등록번호 |
US-8288660
(2012-10-16)
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발명자
/ 주소 |
|
출원인 / 주소 |
- International Business Machines Corporation
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
2 인용 특허 :
6 |
초록
▼
The stopband characteristics of an electromagnetic bandgap structure in a printed circuit board may be preserved by selectively forming slots in an additional conductive layer of the printed circuit board. For example, an electromagnetic bandgap structure may include a layer with a continuous conduc
The stopband characteristics of an electromagnetic bandgap structure in a printed circuit board may be preserved by selectively forming slots in an additional conductive layer of the printed circuit board. For example, an electromagnetic bandgap structure may include a layer with a continuous conductive region and another layer with a periodically patterned region having a plurality of spaced-apart patches interconnected by branches. Additional conductive layers may be included within the printed circuit board without neutralizing the bandgap by forming slots in the conductive layers in general alignment with spaces between the patches.
대표청구항
▼
1. A multi-layer circuit board, comprising: a first conductive layer having a substantially continuous region;a second conductive layer spaced from the first conductive layer with a dielectric material between the first and second conductive layers, the second conductive layer having a periodically
1. A multi-layer circuit board, comprising: a first conductive layer having a substantially continuous region;a second conductive layer spaced from the first conductive layer with a dielectric material between the first and second conductive layers, the second conductive layer having a periodically patterned region including a plurality of spaced-apart conductive patches interconnected by conductive branches, the substantially continuous region of the first layer spanning at least the periodically patterned region of the second layer; anda third conductive layer spaced from the second conductive layer in a direction away from the first conductive layer with a dielectric material between the second and third conductive layers, the third conductive layer having a slotted region including slots aligned with spaces between the patches in the periodically patterned region, wherein the first and third conductive layers are the nearest conductive layers on either side of the second conductive layer. 2. The multi-layer circuit board of claim 1, wherein one of the first and second conductive layers is a power layer and the other of the first and second conductive layers is a ground layer. 3. The multi-layer circuit board of claim 2, wherein the third conductive layer is another ground layer or another power layer. 4. The multi-layer circuit board of claim 2, further comprising an outer layer having a plurality of circuits formed thereon, each circuit being coupled by vias to the power layer and to the ground layer. 5. The multi-layer circuit board of claim 2, further comprising one or more additional ground layers. 6. The multi-layer circuit board of claim 1, wherein the slotted region spans a smaller area than the patterned region. 7. The multi-layer circuit board of claim 6, further comprising aggressor and victim circuits disposed on another layer within the span of the slotted region. 8. The multi-layer circuit board of claim 1, wherein the slotted region of the third conductive layer substantially mirrors the periodically patterned region of the second conductive layer. 9. The multi-layer circuit board of claim 1, wherein the conductive patches are arranged in a rectangular array with substantially evenly-spaced patches. 10. The multi-layer circuit board of claim 1, wherein the substantially continuous region is a solid metal region. 11. The multi-layer circuit board of claim 1, wherein one or more of the first, second, and third conductive layers comprise a homogenous metal or metal alloy. 12. A method of forming a multi-layer circuit board, comprising: forming a first conductive layer including a substantially continuous region;forming a second conductive layer spaced from the first conductive layer;forming a periodically patterned region on the second conductive layer including a plurality of spaced-apart conductive patches interconnected by conductive branches and spanning at least the substantially continuous region of the first layer;forming a third conductive layer spaced from the second conductive layer in a direction away from the first conductive layer;forming a slotted region in the third conductive layer, including slots aligned with spaces between the patches in the periodically patterned region of the second layer, the periodically patterned region of the second layer spanning at least the slotted region of the third layer; andforming the layers of the multi-layer circuit board such that the first and third conductive layers are the nearest conductive layers on either side of the second conductive layer. 13. The method of claim 12, further comprising: forming the second conductive layer as a solid metal layer; andforming the periodically patterned region of the second conductive layer by etching the spaced-apart conductive patches interconnected by conductive branches in the solid metal layer. 14. The method of claim 12, further comprising: forming the third conductive layer as a solid metal layer; andforming the slots in the third conductive layer by etching the slots in the solid metal layer at the selected locations. 15. The method of claim 12, further comprising: forming a plurality of circuits on another layer spaced from the first and second layers and within the span of the periodically patterned region of the second layer;selecting an aggressor circuit and a victim circuit from among the plurality of circuits; andforming the slotted region such that the slotted region spans at least the aggressor circuit and the victim circuit. 16. The method of claim 15, further comprising: forming one of the first and second conductive layers in a ground plane;forming the other of the first and second conductive layers in a power plane; andcoupling each circuit to the first and second conductive layers. 17. The method of claim 12, further comprising: forming the patterned region with a larger span than the slotted region. 18. The method of claim 12, further comprising forming the slotted region as a substantial mirror image of the portion of the periodically patterned region opposite the slotted region.
이 특허에 인용된 특허 (6)
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Sanchez, Victor C.; McKinzie, III, William E.; Diaz, Rodolfo E., Broadband antennas over electronically reconfigurable artificial magnetic conductor surfaces.
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Ramprasad, Ramamurthy; Petras, Michael F., Electromagnetic band gap microwave filter.
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Choi,Jinwoo; Swaminathan,Madhavan; Govind,Vinu, Electromagnetic bandgap structure for isolation in mixed-signal systems.
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Choi,Jinwoo; Swaminathan,Madhavan; Govind,Vinu, Mixed-signal systems with alternating impedance electromagnetic bandgap (AI-EBG) structures for noise suppression/isolation.
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McKinzie, III,William E., Systems and methods for blocking microwave propagation in parallel plate structures utilizing cluster vias.
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Daniel Sievenpiper ; Greg Tangonan ; Robert Y. Loo ; James H. Schaffner, Tunable impedance surface.
이 특허를 인용한 특허 (2)
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Choi, Jinwoo, Signal amplification using a reference plane with alternating impedance.
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Choi, Jinwoo, Signal amplification using a reference plane with alternating impedance.
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