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Hardware based dynamic load balancing of message passing interface tasks by modifying tasks 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/46
출원번호 US-0846168 (2007-08-28)
등록번호 US-8312464 (2012-11-13)
발명자 / 주소
  • Arimilli, Lakshminarayana B.
  • Arimilli, Ravi K.
  • Rajamony, Ramakrishnan
  • Speight, William E.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Walder, Jr., Stephen J.
인용정보 피인용 횟수 : 3  인용 특허 : 22

초록

Mechanisms are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waitin

대표청구항

1. A method, in a multiple processor system, for balancing a Message Passing Interface (MPI) workload across a plurality of processors, comprising: receiving a plurality of MPI synchronization operation calls from one or more processors of the plurality of processors;determining if a state of the mu

이 특허에 인용된 특허 (22)

  1. Diard,Franck R., Adaptive load balancing in a multi-processor graphics processing system.
  2. Brenner, Larry Bert; Browning, Luke Matthew, Apparatus and method for periodic load balancing in a multiple run queue system.
  3. Ted Eric Blank ; Tammie Dang ; Fen-Ling Lin ; Randy Mitchell Nakagawa ; Bryan Frederick Smith ; Craig Leonard Sutton ; Darren Benjamin Swank ; Hong Sang Tie ; Dino Carlo Tonelli ; Annie S. T, Apportioning a work unit to execute in parallel in a heterogeneous environment.
  4. Zhang,Bin; Hsu,Meichun; Forman,George, Distributed data clustering system and method.
  5. Hardwick Jonathan C.,GBX, Dynamic load balancing among processors in a parallel computer.
  6. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Rajamony, Ramakrishnan; Speight, William E., Hardware based dynamic load balancing of message passing interface tasks.
  7. Vrba Richard Alan ; Klecka James Stevens ; Fey ; Jr. Kyran Wilfred ; Lamano Larry Leonard ; Mehta Nikhil A., High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors.
  8. Hwang, Cherng-Daw; Wong, Kenley, Method and apparatus for providing a time-division multiplexing (TDM) interface among a high-speed data stream and multiple processors.
  9. Horst Robert W. (Champaign IL), Method and apparatus for synchronizing a plurality of processors.
  10. Kanai,Tatsunori; Maeda,Seiji; Yano,Hirokuni; Yoshii,Kenichiro, Method and system for performing real-time operation.
  11. Arimilli, Lakshminarayana B.; Arimilli, Ravi K.; Rajamony, Ramakrishnan; Speight, William E., Modifying an operation of one or more processors executing message passing interface tasks.
  12. Lee J. William ; Bridge ; Jr. William H., Multi-node fault-tolerant timestamp generation.
  13. Naganuma Jiro (Zama JPX) Ogura Takeshi (Chigasaki JPX), Multiprocessor system and a method of load balancing thereof.
  14. Fukuda Munehiro (Sagamihara JPX) Matsumoto Takashi (Tokyo JPX) Nakada Takeo (Kawaguchi JPX), Multiprocessor system having synchronization control mechanism.
  15. Hardwick Jonathan C.,GBX, Nested parallel language preprocessor for converting parallel language programs into sequential code.
  16. Agrawal Rakesh ; Ho Ching-Tien ; Zaki Mohammed J., Parallel classification for data mining in a shared-memory multiprocessor system.
  17. Gulko,Abraham; Mellor,David, Parallel computing system, method and architecture.
  18. Jones, Terry R.; Watson, Pythagoras C.; Tuel, William; Brenner, Larry; Caffrey, Patrick; Fier, Jeffrey, Parallel-aware, dedicated job co-scheduling within/across symmetric multiprocessing nodes.
  19. Konno Chisato,JPX ; Okochi Toshio,JPX, Program execution control in parallel processor system for parallel execution of plural jobs by selected number of proce.
  20. Cousins, David Bruce; Daily, Matthew Paul; Lirakis, Christopher Burbank, System and method for automatically optimizing heterogenous multiprocessor software performance.
  21. Pronovost,Steve; Gosalia,Anuj B.; Langley,Bryan L.; Nagase,Hideyuki, Systems and methods for scheduling coprocessor resources in a computing system.
  22. Smith Bradley J. (Converse TX), Weighted system and method for spatial allocation of a parallel load.

이 특허를 인용한 특허 (3)

  1. Nadathur, Gokul; Singh, Manpreet; Ho, Grace, Adjustment of threads for execution based on over-utilization of a domain in a multi-processor system by destroying parallizable group of threads in sub-domains.
  2. Nadathur, Gokul; Singh, Manpreet; Ho, Grace, Adjustment of threads for execution based on over-utilization of a domain in a multi-processor system by sub-dividing parallizable group of threads to sub-domains.
  3. Chang, Wooseok; Roh, Kangho; Lee, Jongwon, Storage device and garbage collection method of data storage system having the storage device.
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