[특허]Pipeline architecture for maximum a posteriori (MAP) decoders

Pipeline architecture for maximum a posteriori (MAP) decoders 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03M-013/00
출원번호	US-0045041 (2011-03-10)
등록번호	US-8316285 (2012-11-20)
발명자 / 주소	Hepler, Edward L. Starsinic, Michael F.
출원인 / 주소	InterDigital Technology Corporation
대리인 / 주소	Volpe and Koenig, P.C.
인용정보	피인용 횟수 : 0 인용 특허 : 35

초록 ▼

Methods and apparatus for performing error correction of data bits are disclosed. A forward metric calculation may be performed during a first window to generate a first group of calculated data. The first group of calculated data from the forward calculation may be stored in a memory location. A forward metric calculation may be performed during a second window to generate a second group of calculated data. The first group of calculated data may be read from the memory location and the second group of calculated data may be stored in the same memory location. The first group of calculated data may be used to calculate reverse metrics.

대표청구항 ▼

1. A method for performing error correction of data bits, the method comprising: receiving one or more data bits;during a first window, performing a forward metric calculation on the one or more data bits to generate a first group of calculated data;storing the first group of calculated data in a first memory location; andduring a second window, performing a forward metric calculation on the one or more data bits to generate a second group of calculated data;reading out the first group of calculated data from the first memory location and storing the second group of calculated data to a location in the first memory from which the first group of calculated data was read out; andusing the first group of calculated data to calculate reverse metrics during the second window. 2. The method of claim 1, further comprising: performing an output calculation on the second group of calculated data. 3. The method of claim 1, wherein the performing the forward metric calculation on the one or more data bits further includes: performing the forward metric calculation in a predetermined order. 4. The method of claim 3, wherein the reading the first group of calculated data from the first memory location further includes: reading the first group of calculated data from the first memory location in a reverse order of the predetermined order. 5. The method of claim 1, further comprising: performing a gamma calculation on the one or more data bits prior to performing the forward metric calculation on the one or more data bits. 6. The method of claim 1, further comprising: calculating an extrinsic value based on the first group of calculated data; andstoring the extrinsic value in a second memory location, the second memory location being linked to the first memory location. 7. An apparatus configured to perform error correction of data bits, the apparatus comprising: a receiver configured to receive one or more data bits;a processor configured to, during a first time period, window, perform a forward metric calculation on the one or more data bits to generate a first group of calculated data;a first memory location configured to, during the first time period, store the first group of calculated data; andthe processor further configured to, during a second window: perform a forward metric calculation on the one or more data bits to generate a second group of calculated data;read out the first group of calculated data from the first memory location and store the second group of calculated data to a location in the first memory from which the first group of calculated data was read out; anduse the first group of calculated data to calculate reverse metrics during the second window. 8. The apparatus of claim 7, wherein the processor is further configured to perform an output calculation on the second group of calculated data. 9. The apparatus of claim 7, wherein the processor is further configured to perform the forward metric calculation on the one or more data bits in a predetermined order. 10. The apparatus of claim 9, wherein the processor is further configured to read the first group of calculated data from the first memory location in a reverse order of the predetermined order. 11. The apparatus of claim 7, wherein the processor is further configured to perform a gamma calculation on the one or more data bits prior to performing the forward metric calculation on the one or more data bits. 12. The apparatus of claim 7, further including a second memory location, the second memory location being linked to the first memory location, wherein: the processor is further configured to calculate an extrinsic value based on the first group of calculated data; andthe second memory location is configured to store the extrinsic value.

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