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Configuration context switcher with a latch

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/173
  • H03K-019/00
  • H01L-025/00
출원번호 US-0089265 (2011-04-18)
등록번호 US-8324931 (2012-12-04)
발명자 / 주소
  • Voogel, Martin
  • Redgrave, Jason
  • Chandler, Trevis
출원인 / 주소
  • Tabula, Inc.
대리인 / 주소
    Adeli & Tollen, LLP
인용정보 피인용 횟수 : 12  인용 특허 : 224

초록

Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circ

대표청구항

1. An integrated circuit (“IC”) comprising: a configurable circuit for configurably performing one of a plurality of operations based on configuration data;a plurality of storage circuits for storing a plurality of configuration data sets for the configurable circuit; andan interconnect circuit for

이 특허에 인용된 특허 (224)

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  2. Voogel, Martin; Teig, Steven; Chanack, Thomas S.; Caldwell, Andrew; Ko, Jung; Chandler, Trevis, Configurable storage elements.
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  4. Chandler, Trevis; Entjer, Joe; Voogel, Martin; Redgrave, Jason, Configuration context switcher with a clocked storage element.
  5. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Configuration context switcher with a latch.
  6. Voogel, Martin; Redgrave, Jason; Chandler, Trevis, Configuration context switcher with a latch.
  7. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  8. Redgrave, Jason, Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements.
  9. Huang, Randy R.; Voogel, Martin; Hu, Jingcao; Teig, Steven, System and method for reducing reconfiguration power.
  10. Shu, LeeLean; Tung, Chenming W.; Lee, Hsin You S., Systems and methods of sectioned bit line memory arrays.
  11. Shu, Lee-Lean; Tung, Chenming W.; Lee, Hsin You S., Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features.
  12. Shu, LeeLean; Tung, Chenming W.; Lee, Hsin You S., Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features.
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