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A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as

A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.

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1. A voter tester comprising: a first set of K input terminals adapted to receive K test signals; anda second set of N input terminals adapted to receive N channel signals generated by N redundant circuits; wherein in response to logic combinations of the test signals, the voter tester generates M o

1. A voter tester comprising: a first set of K input terminals adapted to receive K test signals; anda second set of N input terminals adapted to receive N channel signals generated by N redundant circuits; wherein in response to logic combinations of the test signals, the voter tester generates M output signals, and wherein in response to at least one logic combination of the test signals, a voter responsive to the voter tester generates Q voted output signals, wherein N, K, M and Q are integer numbers. 2. The voter tester of claim 1, wherein each of the M output signals is defined by a different one of the N redundant channel signals. 3. The voter tester of claim 1 wherein the voter tester further comprises a test enable/disable signal, wherein if said test enable/disable signal is in a first logic state the voter generates a voted output signal, and if said test enable/disable signal is in a second logic state the voter generates an output signal supplied by one of the N redundant input circuits. 4. The voter tester of claim 1 wherein the voter tester generates N output signals. 5. The voter tester of claim 1 wherein the Q output signals of the voter comprise an output signal defined by a majority of the M signals received from the voter tester. 6. The voter tester of claim 1 further comprising a serial interface port adapted to receive the K test signals serially. 7. The voter tester of claim 1 further comprising a parallel interface adapted to receive the K test signals in parallel. 8. The voter tester of claim 1 further comprising a plurality of single event transient hardened logic gates. 9. The voter tester of claim 1 further comprising: substantially similar delay paths each disposed between one of the N input channel signals and an associated one of the M output signals. 10. A method of testing N redundant circuits feeding a voter circuit, the method comprising: receiveng K test signals;receiving N channel signals generated by the N redundant circuits;enabling the voter tester circuit to generate M output signals; andenabling the voter circuit to generate Q voted output signals in response to the M output signals and at least one logic combination of the test signals, wherein N, M, K and O are integer numbers. 11. The method of claim 10 further comprising: enabling the voter circuit to generate a voted output signal in response to a first logic state of an enabling/disabling signal; andenabling the voter circuit to generate an output signal supplied by one of the redundant channels in response to a second logic state of the enabling/disabling signal. 12. The method of claim 10 wherein K is an odd integer number equal to N+1. 13. The method of claim 10 further comprising receiving the K test signals via one of a serial interface port and a parallel interface port. 14. The method of claim 11 further comprising: delivering the enabling/disabling signal to at least one single-event transient hardened logic gate. 15. The method of claim 10 further comprising: forming substantially similar delay paths each disposed between a different one of the N input channel signals and an associated one of the M output signals. 16. A pulse-width modulated DC-DC converter comprising: an inductor;a transistor adapted to supply current to the inductor;a voter circuit coupled to a gate terminal of the transistor;N-redundant circuits supplying N channel signals; anda voter tester comprising: a first set of input terminals adapted to receive at least one test signal; anda second set of input terminals adapted to receive a plurality of channel signals generated by redundant circuits; wherein in response to logic combinations of the at least one test signal, the voter tester generates output signals defined by the plurality of channel signals, andwherein in response to the output signals of the voter tester, the voter circuit generates a voted output signal.