Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-027/095
H01L-029/47
H01L-029/812
H01L-031/07
출원번호
US-0492670
(2009-06-26)
등록번호
US-8330244
(2012-12-11)
발명자
/ 주소
Zhang, Qingchun
Ryu, Sei-Hyung
Agarwal, Anant
출원인 / 주소
Cree, Inc.
대리인 / 주소
Myers Bigel Sibley & Sajovec
인용정보
피인용 횟수 :
5인용 특허 :
156
초록▼
A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of
A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.
대표청구항▼
1. A semiconductor device, comprising: a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined;a plurality of spaced apart first doped regions arranged within the active region, the plurality of first doped regions
1. A semiconductor device, comprising: a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined;a plurality of spaced apart first doped regions arranged within the active region, the plurality of first doped regions having a second conductivity type that is opposite the first conductivity type, having a first dopant concentration, and defining a plurality of exposed portions of the semiconductor layer within the active region, wherein the plurality of first doped regions are arranged as islands in the semiconductor layer; anda second doped region in the active region of the semiconductor layer and between and spaced apart from the plurality of spaced apart first doped regions, the second doped region having the second conductivity type and having a second dopant concentration that is greater than the first dopant concentration. 2. The semiconductor device of claim 1, wherein the islands comprise circular islands. 3. The semiconductor device of claim 1, wherein the islands have irregular shapes. 4. The semiconductor device of claim 1, wherein the islands have rectangular shapes. 5. The semiconductor device of claim 1, wherein the islands have polygonal shapes. 6. The semiconductor device of claim 1, wherein the semiconductor layer comprises an epitaxial layer of silicon carbide. 7. The semiconductor device of claim 1, wherein the plurality of first doped regions and the second doped region are located at the surface of the semiconductor layer, and wherein a ratio of a surface area occupied by the plurality of first doped regions and the second doped region to a total surface area of the active region of the diode is about 0.3. 8. The semiconductor device of claim 1, the device further comprising a metal layer on the surface of the semiconductor layer, the metal layer forming a Schottky junction with the defined exposed portions of the semiconductor layer and forming an ohmic contact with the second doped region, wherein a turn-on voltage of a p-n junction between the second doped region and the semiconductor layer is higher than a turn-on voltage of the Schottky junction between the metal layer and the exposed portions of the semiconductor layer. 9. The semiconductor device of claim 1, the device further comprising a metal layer on the surface of the semiconductor layer, the metal layer forming a Schottky junction with the defined exposed portions of the semiconductor layer and forming an ohmic contact with the second doped region, wherein the first doped regions have a thickness and dopant concentration such that punch-through of p-n junctions between the first doped regions and the semiconductor layer occurs at a lower voltage than breakdown of the Schottky junction between the metal layer and the exposed portions of the semiconductor layer. 10. A semiconductor device, comprising: a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined;a plurality of spaced apart first doped regions arranged within the active region, the plurality of first doped regions having a second conductivity type that is opposite the first conductivity type, having a first dopant concentration, and defining a plurality of exposed portions of the semiconductor layer within the active region, wherein the plurality of first doped regions are arranged as islands in the semiconductor layer;a second doped region in the active region of the semiconductor layer, the second doped region having the second conductivity type and having a second dopant concentration that is greater than the first dopant concentration; anda metal layer on the surface of the semiconductor layer, the metal layer forming a Schottky junction with the defined exposed portions of the semiconductor layer and forming an ohmic contact with the second doped region,wherein the metal layer comprises a first metal region in contact with the exposed portions of the semiconductor layer and the first doped region and a second metal region in contact with the second doped region, wherein the first metal region comprises a metal different from the second metal region. 11. The semiconductor device of claim 10, wherein the semiconductor layer comprises a silicon carbide semiconductor layer. 12. The semiconductor device of claim 11, wherein the first doped region comprises p-type silicon carbide having a dopant concentration of from about 1×1017 to about 1×1018 cm−3, and the second doped region comprises p-type silicon carbide having a dopant concentration of greater than about 5×1018 cm−3. 13. A semiconductor device, comprising: a semiconductor layer having a first conductivity type and having a surface in which an active region of the semiconductor device is defined;a plurality of spaced apart first doped regions arranged within the active region, the plurality of first doped regions having a second conductivity type that is opposite the first conductivity type, having a first dopant concentration, and defining a plurality of exposed portions of the semiconductor layer within the active region, wherein the plurality of first doped regions are arranged as islands in the semiconductor layer;a second doped region in the active region of the semiconductor layer and spaced apart from the plurality of spaced apart first doped regions, the second doped region having the second conductivity type and having a second dopant concentration that is greater than the first dopant concentration; andan edge termination region, wherein the first doped regions have a thickness and dopant concentration such that punch-through of p-n junctions between the first doped regions and the semiconductor layer occurs at a lower voltage than a breakdown voltage of the edge termination region. 14. A semiconductor device comprising: a semiconductor layer having a first conductivity type;a metal contact on the semiconductor layer and forming a Schottky junction with the semiconductor layer;a semiconductor region in the semiconductor layer and having a second conductivity type, opposite the first conductivity type, and comprising a plurality of first doped regions arranged as islands in the semiconductor layer;wherein the first doped regions and the semiconductor layer form respective p-n junctions in parallel with the Schottky junction;wherein the p-n junctions are configured to generate a depletion region in the semiconductor layer adjacent the Schottky junction when the Schottky junction is reversed biased to limit reverse leakage current through the Schottky junction; andwherein the p-n junctions are further configured such that punch-through of the p-n junctions occurs at a lower voltage than a breakdown voltage of the Schottky junction. 15. The semiconductor device of claim 14, wherein the plurality of first doped regions and a second doped region are located at the surface of the semiconductor layer, and wherein a ratio of a surface area occupied by the plurality of first doped regions and the second doped region to a total surface area of the active region of the diode is between about 0.02 and 0.4. 16. The semiconductor device of claim 15, wherein the plurality of first doped regions and the second doped region are located at the surface of the semiconductor layer, and wherein a ratio of a surface area occupied by the plurality of first doped regions and the second doped region to a total surface area of the active region of the diode is about 0.3. 17. The semiconductor device of claim 14, wherein a turn-on voltage of a p-n junction between a second doped region and the semiconductor layer is higher than a turn-on voltage of the Schottky junction between the metal layer and the exposed portions of the semiconductor layer. 18. The semiconductor device of claim 14, wherein the metal layer comprises a first metal region in contact with the exposed portions of the semiconductor layer and the first doped region and a second metal region in contact with a second doped region, wherein the first metal region comprises a metal different from the second metal region. 19. The semiconductor device of claim 14, wherein the semiconductor layer comprises a silicon carbide semiconductor layer. 20. The semiconductor device of claim 14, wherein the first doped region comprises p-type silicon carbide having a dopant concentration of from about 1×1017 to about 1×1018 cm−3, and a second doped region comprises p-type silicon carbide having a dopant concentration of greater than about 5×1018 cm−3.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (156)
Smith, Richard Peter, Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment.
Edmond John A. (Apex NC) Dmitriev Vladimir (Fuquay-Varina NC) Irvine Kenneth (Cary NC), Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices.
Gardner Mark I. ; Hause Fred N. ; Fulford ; Jr. H. Jim, CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMO.
Bakowski Mietek,SEX ; Gustafsson Ulf,SEX ; Rottner Kurt,SEX ; Savage Susan,SEX, Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge.
Brown Dale M. (Schenectady NY) Michon Gerald J. (Waterford NY) Krishnamurthy Vikram B. (Latham NY) Kretchmer James W. (Ballston Spa NY), Fabrication of silicon carbide integrated circuits.
Khan Muhammed A. (White Bear Lake) VanHove James M. (Eagan) Kuznia Jon N. (Fridley) Olson Donald T. (Circle Pines MN), High electron mobility transistor with GaN/AlxGa1-xN heterojunctions.
Shimoida,Yoshio; Kaneko,Saichirou; Tanaka,Hideaki; Hoshi,Masakatsu; Throngnumchai,Kraisom; Mihara,Teruyoshi; Hayashi,Tetsuya, High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode.
Miyata Koichi (Kobe JPX) Saito Kimitsugu (Kobe NC JPX) Dreifus David L. (Cary NC) Stoner Brian R. (Raleigh NC), Highly oriented diamond film field-effect transistor.
Kong Hua-Shuang (Raleigh NC) Glass Jeffrey T. (Apex NC) Davis Robert F. (Raleigh NC), Homoepitaxial growth of Alpha-SiC thin films and semiconductor devices fabricated thereon.
Moise Theodore S. ; Xing Guoqiang ; Visokay Mark ; Gaynor Justin F. ; Gilbert Stephen R. ; Celii Francis ; Summerfelt Scott R. ; Colombo Luigi, Integrated circuit and method.
Smrtic Mark A. (Stoneham MA) Molnar George M. (Flemington NJ) Lapham Jerome F. (Groton MA), Integrated circuit metal-oxide-metal capacitor and method of making same.
Shah,Pankaj B., Interacting current spreader and junction extender to increase the voltage blocked in the off state of a high power semiconductor device.
Smayling Michael C. (Missouri City TX) Torreno ; Jr. deceased Manuel J. (late of Houston TX by Arlene Torreno ; executrix) Falessi George (Villeneuve-Loubet FRX), LDMOS transistor with self-aligned source/backgate and photo-aligned gate.
Williams Richard K. ; Darwish Mohamed ; Grabowski Wayne ; Cornell Michael E., Low resistance power MOSFET or other device containing silicon-germanium layer.
Harris Christopher,SEX ; Konstantinov Andrei,SEX ; Janzen Erik,SEX, Method for introduction of an impurity dopant in SiC, a semiconductor device formed by the method and a use of highly d.
Tsui Paul G. Y. ; Tseng Hsing-Huang ; Bhat Navakanta ; Chen Ping, Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region.
Ghezzo Mario (Ballston Lake NY) Chow Tat-Sing P. (Schenectady NY) Kretchmer James W. (Ballston Spa NY) Saia Richard J. (Schenectady NY) Hennessy William A. (Niskayuna NY), Method of fabricating a self-aligned DMOS transistor device using SiC and spacers.
Singh Ranbir ; Agarwal Anant K. ; Ryu Sei-Hyung, Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices.
Paul Chang ; Geeng-Chuan Chern ; Wayne Y. W. Hsueh ; Vladimir Rodov, Method of fabricating power rectifier device to vary operating parameters and resulting device.
Kong Hua-Shuang (Raleigh NC) Carter ; Jr. Calvin H. (Cary NC), Method of improving mechanically prepared substrate surfaces of alpha silicon carbide for deposition of beta silicon car.
Khan Muhammad A. (White Bear Lake MN) VanHove James M. (Eagan MN) Kuznia Jon N. (Fridley MN) Olson Donald T. (Circle Pines MN), Method of making a high electron mobility transistor.
Kumar Rajesh,JPX ; Naito Masami,JPX ; Nakamura Hiroki,JPX ; Takeuchi Yuichi,JPX, Method of manufacturing silicon carbide semiconductor device using active and inactive ion species.
Sei-Hyung Ryu ; Joseph J. Sumakeris ; Anant K. Agarwal ; Ranbir Singh, Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation.
Korman Charles S. (Schenectady NY) Baliga Bantval J. (Raleigh NC) Chang Hsueh-Rong (Scotia NY), Multicellular FET having a Schottky diode merged therewith.
Anderson Wayne A. (Hamburg NY) Jia Quanxi (Los Alamos NM) Yi Junsin (Amherst NY) Chang Lin-Huang (Tonawanda NY), Nanocrystalline layer thin film capacitors.
Agarwal Anant K. (Monroeville PA) Siergiej Richard R. (Irwin PA) Brandt Charles D. (Mt. Lebanon PA) White Marvin H. (Bethlehem PA), Non-volatile random access memory cell constructed of silicon carbide.
Narwankar Pravin K. ; Sahin Turgut ; Redinbo Gregory F. ; Liu Patricia M. ; Tran Huyen T., Post deposition treatment of dielectric films for interface control.
Rodov, Vladimir; Chang, Paul; Bao, Jianren; Hsueh, Wayne Y. W.; Chiang, Arthur Ching-Lang; Chern, Geeng-Chuan, Power diode having improved on resistance and breakdown voltage.
Ryu, Sei-Hyung; Agarwal, Anant; Das, Mrinal Kanti; Lipkin, Lori A.; Palmour, John W.; Singh, Ranbir, SILICON CARBIDE POWER METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A SHORTING CHANNEL AND METHODS OF FABRICATING SILICON CARBIDE METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING.
Suvorov Alexander ; Palmour John W. ; Singh Ranbir, Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion.
Ghezzo Mario ; Chow Tat-Sing Paul ; Kretchmer James William ; Saia Richard Joseph ; Hennessy William Andrew, Self-aligned transistor device including a patterned refracting dielectric layer.
Friedrichs, Peter; Peters, Dethard; Schoerner, Reinhold, Semiconductor device made from silicon carbide with a Schottky contact and an ohmic contact made from a nickel-aluminum material.
Schorner Reinhold,DEX ; Stephani Dietrich,DEX ; Peters Dethard,DEX ; Friedrichs Peter,DEX, Semiconductor structure having a predetermined alpha-silicon carbide region, and use of this semiconductor structure.
Bakowsky Mietek,SEX ; Bijlenga Bo,SEX ; Gustafsson Ulf,SEX ; Harris Christopher,SEX ; Savage Susan,SEX, SiC Semiconductor device comprising a pn Junction with a voltage absorbing edge.
Shah, Pankaj B., Silicon carbide (SiC) gate turn-off (GTO) thyristor structure for higher turn-off gain and larger voltage blocking when in the off-state.
Ryu, Sei-Hyung, Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same.
Davis Robert F. (Raleigh NC) Carter ; Jr. Calvin H. (Raleigh NC) Hunter Charles E. (Durham NC), Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide.
Degenhardt Charles R. (The Procter & Gamble Company ; Miami Valley Laboratories ; P.O. Box 398707 Cincinnati OH 45239-8707) Kozikowski Barbara A. (The Procter & Gamble Company ; Miami Valley Laborato, Use of a carboxy-substituted polymer to inhibit plaque formation without tooth staining.
Edmond John A. (Cary NC) Bulman Gary E. (Cary NC) Kong Hua-Shuang (Raleigh NC) Dmitriev Vladimir (Fuquay-Varina NC), Vertical geometry light emitting diode with group III nitride active layer and extended lifetime.
Kim, Hyun-Ju; Jang, Jae-June; Chang, Hoon; Kim, Jae-Ho; Cho, Kyu-Heon, Semiconductor device having depletion region for improving breakdown voltage characteristics.
Arthur, Stephen Daley; Bolotnikov, Alexander Viktorovich; Losee, Peter Almern; Matocha, Kevin Sean; Saia, Richard Joseph; Stum, Zachary Matthew; Stevanovic, Ljubisa Dragoljub; Kishore, Kuna Venkat Satya Rama; Kretchmer, James William, Semiconductor device with junction termination extension.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.