초록 ▼

An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a

An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material.

대표청구항 ▼

1. An interconnect structure comprising: a first interconnect level including a first dielectric material having at least one conductive feature embedded therein, said at least one conductive feature having a via gouging feature located therein;a patterned metallic capping layer located atop some, b

1. An interconnect structure comprising: a first interconnect level including a first dielectric material having at least one conductive feature embedded therein, said at least one conductive feature having a via gouging feature located therein;a patterned metallic capping layer located atop some, but not all, portions of the at least one conductive feature;a patterned dielectric capping layer located atop the patterned metallic capping layer and portions of the first dielectric material;a second interconnect level including a second dielectric material having at least one conductively filled line embedded in a porous dielectric material located atop and connected to an underlying conductively filled via embedded in a non-porous third dielectric material, wherein said first and second dielectric materials comprise the same porous low k dielectric,wherein the metallic capping layer extends onto a first diffusion barrier without extending onto the first dielectric material,wherein the first diffusion barrier lines at least one opening within the first dielectric material, and is affixed on an exposed wall portion of the first dielectric material, andwherein a lower portion of said conductively filled via located in proximity to the patterned dielectric capping layer includes a multi-layered liner comprising: a second diffusion barrier from a patterned surface of the second dielectric material outwards;a multi-material layer including a first material layer comprising residue from said patterned dielectric capping layer, anda second material layer comprising residue from said patterned metallic capping layer; anda hard mask comprising multilayered stacks of oxynitride; anda third diffusion barrier formed on all exposed surfaces of the one opening within the first dielectric material and on top of the hard mask comprising a multilayered stack with at least one layer of tantalum, at least one layer of ruthenium, and at least one layer of titanium. 2. The semiconductor structure of claim 1 wherein: said first and second dielectric materials comprise the same or different low k dielectric having a dielectric constant of about 4.0 or less;the second diffusion barrier is in contact with the second dielectric materials, the multi-material layer being located on the sidewalls of the second diffusion barrier; andthe third diffusion barrier has an upper surface that is coplanar with the second dielectric materials. 3. The semiconductor structure of claim 1 wherein said first and second dielectric materials comprise the same or different porous low k dielectric having a dielectric constant of about 2.8 or less. 4. The semiconductor structure of claim 1 wherein said first and second dielectric materials are the same or different and comprise at least one of SiO2, a silsesquioxane, a C doped oxide that include atoms of Si, C, O and H, and a thermosetting polyarylene ether. 5. The semiconductor structure of claim 1 wherein said patterned dielectric capping layer comprises one of SiC, Si4NH3, SiO2, a carbon doped oxide, and a nitrogen and hydrogen doped silicon carbide SiC(N,H). 6. The semiconductor structure of claim 1 wherein said patterned metallic capping layer comprises one from the group consisting of Co, Ir and Ru in pure form or alloyed with at least one from the group consisting of W, B, P, Mo and Re. 7. The semiconductor structure of claim 6, wherein said patterned metallic capping layer is Co-containing. 8. The interconnect structure of claim 1 wherein said conductively filled line and said conductively filled and said via gouging feature are filled with the same interconnect conductive material. 9. The interconnect structure of claim 8 wherein said interconnect conductive material is comprised of Cu or a Cu-containing alloy. 10. The interconnect structure of claim 1 wherein said first material layer comprises atoms of silicon and nitrogen. 11. The interconnect structure of claim 1 wherein said second material layer comprises atoms selected from the group consisting of Co, Ir and Ru. 12. The interconnect structure of claim 1 wherein said metal-containing hard mask comprises one of Ru, Ta and Ti.