$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Vector processor system

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
출원번호 US-0475393 (2009-05-29)
등록번호 US-8356144 (2013-01-15)
발명자 / 주소
  • Hessel, Richard
  • Keltcher, Chetana N.
  • Tuck, Nathan Daniel
  • Van Dyke, Korbin S.
출원인 / 주소
  • Hessel, Richard
인용정보 피인용 횟수 : 129  인용 특허 : 2

초록

A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces co

대표청구항

1. A system comprising: a plurality of floating point execution units compatible with operation according to a plurality of execution threads;a plurality of memory channels each enabled to access at least one Dynamic Random Accessible read/write Memory (DRAM) element;a memory buffer switch unit coup

이 특허에 인용된 특허 (2)

  1. Longhenry Brian E. ; Thome Gary W. ; Thayer John S., Line drawing using operand routing and operation selective multimedia extension unit.
  2. Hessel, Richard Edward; Tuck, Nathan Daniel; Van Dyke, Korbin S.; Keltcher, Chetana N., Vector processor.

이 특허를 인용한 특허 (129)

  1. Finkbeiner, Timothy P.; Hush, Glen E.; Pinney, David L., Accessing data in memory.
  2. Finkbeiner, Timothy P.; Hush, Glen E.; Pinney, David L., Accessing data in memory.
  3. Lea, Perry V.; Rosti, Shawn, Apparatus and methods for debugging on a memory device.
  4. Lea, Perry V., Apparatus and methods for in data path compute operations.
  5. Murphy, Richard C., Apparatuses and methods for cache invalidate.
  6. Murphy, Richard C., Apparatuses and methods for cache invalidate.
  7. Manning, Troy A., Apparatuses and methods for comparing data patterns in memory.
  8. Murphy, Richard C., Apparatuses and methods for compute enabled cache.
  9. La Fratta, Patrick A., Apparatuses and methods for converting a mask to an index.
  10. La Fratta, Patrick A., Apparatuses and methods for converting a mask to an index.
  11. Hush, Glen E., Apparatuses and methods for data movement.
  12. Lea, Perry V.; Hush, Glen E., Apparatuses and methods for data movement.
  13. La Fratta, Patrick A.; Shawver, James J., Apparatuses and methods for data transfer from sensing circuitry to a controller.
  14. La Fratta, Patrick A.; Shawver, James J., Apparatuses and methods for data transfer from sensing circuitry to a controller.
  15. Finkbeiner, Timothy P.; Hush, Glen E.; Murphy, Richard C., Apparatuses and methods for determining population count.
  16. Wheeler, Kyle B., Apparatuses and methods for identifying an extremum value stored in an array of memory cells.
  17. Lea, Perry V.; Murphy, Richard C., Apparatuses and methods for in-memory operations.
  18. Manning, Troy A.; Murphy, Richard C., Apparatuses and methods for parity determination using sensing circuitry.
  19. Manning, Troy A.; Murphy, Richard C., Apparatuses and methods for parity determination using sensing circuitry.
  20. Willcock, Jeremiah J.; Pinney, David L., Apparatuses and methods for partitioned parallel data movement.
  21. Manning, Troy A., Apparatuses and methods for performing an exclusive or operation using sensing circuitry.
  22. Manning, Troy A., Apparatuses and methods for performing compare operations using sensing circuitry.
  23. Manning, Troy A., Apparatuses and methods for performing compare operations using sensing circuitry.
  24. Manning, Troy A., Apparatuses and methods for performing compare operations using sensing circuitry.
  25. Manning, Troy A., Apparatuses and methods for performing compare operations using sensing circuitry.
  26. Zawodny, Jason T.; Tiwari, Sanjay, Apparatuses and methods for performing corner turn operations using sensing circuitry.
  27. Zawodny, Jason T.; Tiwari, Sanjay, Apparatuses and methods for performing corner turn operations using sensing circuitry.
  28. Zawodny, Jason T.; Tiwari, Sanjay, Apparatuses and methods for performing corner turn operations using sensing circuitry.
  29. Manning, Troy A.; Murphy, Richard C., Apparatuses and methods for performing invert operations using sensing circuitry.
  30. Hush, Glen E., Apparatuses and methods for performing logical operations using sensing circuitry.
  31. Hush, Glen E., Apparatuses and methods for performing logical operations using sensing circuitry.
  32. Hush, Glen E.; Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  33. Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  34. Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  35. Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  36. Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  37. Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  38. Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  39. Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry.
  40. Hush, Glen E.; Manning, Troy A., Apparatuses and methods for performing logical operations using sensing circuitry in a memory device.
  41. La Fratta, Patrick A.; Lovitt, Jesse F.; Hush, Glen E.; Finkbeiner, Timothy P., Apparatuses and methods for random number generation.
  42. La Fratta, Patrick A.; Lovitt, Jesse F.; Hush, Glen E.; Finkbeiner, Timothy P., Apparatuses and methods for random number generation.
  43. Hush, Glen E., Apparatuses and methods for shifting data.
  44. Hush, Glen E., Apparatuses and methods for shifting data.
  45. Penney, Daniel B.; Venkata, Harish N.; Perry, Guy S., Apparatuses and methods for storing a data value in a sensing circuitry element.
  46. Penney, Daniel B.; Venkata, Harish N.; Perry, Guy S., Apparatuses and methods for storing a data value in a sensing circuitry element.
  47. La Fratta, Patrick A., Apparatuses and methods for storing a data value in multiple columns.
  48. La Fratta, Patrick A., Apparatuses and methods for storing a data value in multiple columns of an array corresponding to digits of a vector.
  49. Zawodny, Jason T.; Hush, Glen E., Apparatuses and methods to reverse data stored in memory.
  50. Penney, Daniel B.; Venkata, Harish N., Apparatuses and methods to selectively perform logical operations.
  51. Lea, Perry V.; Manning, Troy A., Bank to bank data transfer.
  52. Penney, Daniel B.; Perry, Guy S.; Venkata, Harish N.; Hush, Glen E., Column repair in memory.
  53. Tiwari, Sanjay, Comparison operations in memory.
  54. Tiwari, Sanjay, Comparison operations in memory.
  55. Tiwari, Sanjay, Comparison operations in memory.
  56. Tiwari, Sanjay, Comparison operations in memory.
  57. Wheeler, Kyle B.; Manning, Troy A.; Murphy, Richard C., Comparison operations on logical representations of values in memory.
  58. Willcock, Jeremiah J., Computing reduction and prefix sum operations in memory.
  59. Willcock, Jeremiah J., Computing reduction and prefix sum operations in memory.
  60. Willcock, Jeremiah J.; Hush, Glen E., Control of sensing components in association with performing operations.
  61. Zawodny, Jason T.; Tiwari, Sanjay; Murphy, Richard C., Data gathering in memory.
  62. Zawodny, Jason T.; Tiwari, Sanjay; Murphy, Richard C., Data gathering in memory.
  63. Willcock, Jeremiah J., Data replication.
  64. Willcock, Jeremiah J., Data shift apparatuses and methods.
  65. Willcock, Jeremiah J., Data shift apparatuses and methods.
  66. Tiwari, Sanjay, Data shift by elements of a vector in memory.
  67. Tiwari, Sanjay, Data shift by elements of a vector in memory.
  68. Tiwari, Sanjay, Data shift by elements of a vector in memory.
  69. Cowles, Timothy B.; Bodily, Steven M., Data shifting.
  70. Cowles, Timothy B.; Bodily, Steven M., Data shifting.
  71. Cowles, Timothy B.; Bodily, Steven M., Data shifting.
  72. Wheeler, Kyle B.; Finkbeiner, Timothy P., Data storage layout.
  73. Zawodny, Jason T.; Hush, Glen E.; Murphy, Richard C., Data transfer between subarrays in memory.
  74. Willcock, Jeremiah J.; Hush, Glen E., Data transfer in sensing components.
  75. Wheeler, Kyle B., Division operations for memory.
  76. Wheeler, Kyle B., Division operations for memory.
  77. Tiwari, Sanjay, Division operations in memory.
  78. Tiwari, Sanjay, Division operations in memory.
  79. Tiwari, Sanjay; Wheeler, Kyle B., Division operations on variable length elements in memory.
  80. Tiwari, Sanjay, Element value comparison in memory.
  81. Lea, Perry V., Encryption of executables in computational memory.
  82. Lea, Perry V.; Finkbeiner, Timothy P., Error code calculation on sensing circuitry.
  83. Lea, Perry V.; Finkbeiner, Timothy P., Error code calculation on sensing circuitry.
  84. Wiedemeier, Jeff; Samudrala, Sridhar; Golliver, Roger; Mahurin, Eric W., Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation.
  85. Wheeler, Kyle B.; Murphy, Richard C.; Manning, Troy A.; Klein, Dean A., Generating and executing a control flow.
  86. Wheeler, Kyle B.; Murphy, Richard C.; Manning, Troy A.; Klein, Dean A., Generating and executing a control flow.
  87. Manning, Troy A., Independently addressable memory array address spaces.
  88. Hush, Glen E., Invert operations using sensing circuitry.
  89. Hush, Glen E., Invert operations using sensing circuitry.
  90. Tiwari, Sanjay; Wheeler, Kyle B., Longest element length determination in memory.
  91. Tiwari, Sanjay; Wheeler, Kyle, Loop structure for operations in memory.
  92. Tiwari, Sanjay; Wheeler, Kyle B., Loop structure for operations in memory.
  93. Kim, Hyun-joong; Kim, Soo-hyeong; Shin, Sang-hoon; Jung, Ju-yun; Song, Ho-young; Sohn, Kyo-min; Lee, Hae-suk; Jung, Bu-il; Jeong, Han-vit, Memory device having a shareable error correction code cell array.
  94. Kirsch, Graham; Steadman, Martin, Modified decode for corner turn.
  95. Kirsch, Graham; Steadman, Martin, Modified decode for corner turn.
  96. Leidel, John D.; Wadleigh, Kevin, Multidimensional contiguous memory allocation.
  97. Wheeler, Kyle B.; Finkbeiner, Timothy P.; Willcock, Jeremiah J., Multiple endianness compatibility.
  98. Willcock, Jeremiah J.; Wheeler, Kyle B.; Finkbeiner, Timothy P., Multiple endianness compatibility.
  99. Tiwari, Sanjay, Multiplication operations in memory.
  100. Tiwari, Sanjay, Multiplication operations in memory.
  101. Hush, Glen E., Performing logical operations using sensing circuitry.
  102. Hush, Glen E., Performing logical operations using sensing circuitry.
  103. Hush, Glen E., Performing logical operations using sensing circuitry.
  104. Hush, Glen E., Performing logical operations using sensing circuitry.
  105. Hush, Glen E., Performing logical operations using sensing circuitry.
  106. Murphy, Richard C., Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations.
  107. Alzheimer, Joshua E.; Bell, Debra M., Scan chain operation in sensing circuitry.
  108. Alzheimer, Joshua E., Scan chain operations.
  109. Penney, Daniel B.; Howe, Gary L.; Venkata, Harish N., Shift skip.
  110. Hush, Glen E., Shifting data.
  111. Penney, Daniel B.; Venkata, Harish N.; Perry, Guy S., Shifting data in sensing circuitry.
  112. Penney, Daniel B.; Venkata, Harish N.; Perry, Guy S., Shifting data in sensing circuitry.
  113. Willcock, Jeremiah J.; Hush, Glen E., Shifting data in sensing circuitry.
  114. Willcock, Jeremiah J.; Hush, Glen E., Shifting data in sensing circuitry.
  115. Tiwari, Sanjay, Signed division in memory.
  116. Tiwari, Sanjay, Signed division in memory.
  117. Tiwari, Sanjay, Signed element compare in memory.
  118. Willcock, Jeremiah J., Simulating access lines.
  119. Willcock, Jeremiah J., Simulating access lines.
  120. Wheeler, Kyle B., Sort operation in memory.
  121. Wheeler, Kyle B., Swap operations in memory.
  122. Wheeler, Kyle B., Swap operations in memory.
  123. Leidel, John D., Target architecture determination.
  124. Tiwari, Sanjay, Vector population count determination in memory.
  125. Tiwari, Sanjay; Wheeler, Kyle B., Vertical bit vector shift in memory.
  126. Tiwari, Sanjay; Wheeler, Kyle B., Vertical bit vector shift in memory.
  127. Leidel, John D.; Wheeler, Kyle B., Virtual address table.
  128. Leidel, John D.; Wheeler, Kyle B., Virtual address table.
  129. Leidel, John D.; Rogers, Geoffrey C., Virtual register file.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트