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Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulat

Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal portions, wherein X is between approximately 0.3 and approximately 0.5, to form one or more self-aligned RRAM cells above the first metal electrode; and depositing a second metal electrode layer above the PCMO layer.

대표청구항 ▼

1. A method to form a resistive random access memory (RRAM), comprising: a. forming a first metal electrode layer;b. depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions;c. depositing a Pr1-X CaXMnO3 (PCMO) layer above the insulator a

1. A method to form a resistive random access memory (RRAM), comprising: a. forming a first metal electrode layer;b. depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions;c. depositing a Pr1-X CaXMnO3 (PCMO) layer above the insulator and the metal portions, wherein X is between approximately 0.3 and approximately 0.5;d. forming one or more self-aligned RRAM cells above the first metal electrode; ande. depositing a second metal electrode layer above the PCMO layer. 2. The method of claim 1, comprising depositing and patterning an insulator layer between a wafer and the first metal electrode layer. 3. The method of claim 1, wherein the first metal electrode layer is formed above a wafer. 4. The method of claim 3, comprising forming via holes to connect the first metal electrode layer to circuit on the wafer. 5. The method of claim 4, comprising depositing metal above the via holes. 6. The method of claim 3, comprising depositing an adhesion layer above the first metal electrode layer. 7. The method of claim 5, comprising performing chemical mechanical polishing on the first metal electrode layer. 8. The method of claim 1, wherein the first metal electrode layer comprises one of: platinum, chromium, iridium, ruthenium, nickel, silicides, nickel, titanium. 9. The method of claim 1, comprising depositing a passivation film. 10. The method of claim 9, comprising performing chemical mechanical polishing on the passivated film. 11. The method of claim 1, wherein the forming of the first metal electrode comprises selective plating. 12. A method to form a resistive random access memory (RRAM) array, comprising: a. forming a first metal electrode layer;b. depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions;c. depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal portions;d. forming one or more self-aligned RRAM cells above the first metal electrode; ande. depositing a second metal electrode layer above the PCMO layer. 13. The method of claim 12, comprising forming one or more via holes to connect the first metal electrode layer to a circuit on the wafer. 14. The method of claim 13, comprising depositing metal above the via holes. 15. The method of claim 14, comprising performing chemical mechanical polishing on the first metal electrode layer. 16. The method of claim 12, wherein the forming of the first metal electrode comprises selective plating. 17. A method to form an electronic device comprising a resistive random access memory (RRAM) array, comprising: a. forming a first metal electrode layer;b. depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions;c. depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal portions;d. forming one or more self-aligned RRAM cells above the first metal electrode; ande. depositing a second metal electrode layer above the PCMO layer. 18. The method of claim 17, comprising forming one or more via holes to connect the first metal electrode layer to a circuit on the wafer. 19. The method of claim 17, comprising depositing metal above the via holes. 20. The method of claim 17, comprising performing chemical mechanical polishing on the first metal electrode layer.