IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0243521
(2011-09-23)
|
등록번호 |
US-8384196
(2013-02-26)
|
발명자
/ 주소 |
- Cheng, Zhiyuan
- Fiorenza, James
- Hydrick, Jennifer M.
- Lochtefeld, Anthony J.
- Park, Ji-Soo
- Bai, Jie
- Li, Jizhong
|
출원인 / 주소 |
- Taiwan Semiconductor Manufacturing Company, Ltd.
|
인용정보 |
피인용 횟수 :
27 인용 특허 :
256 |
초록
▼
Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semico
Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.
대표청구항
▼
1. A semiconductor structure comprising: a (110)-surface substrate;an insulator layer over the substrate, the insulator layer having an opening to the substrate; anda cubic semiconductor material in the opening of the insulator layer and adjoining the substrate, the cubic semiconductor material exte
1. A semiconductor structure comprising: a (110)-surface substrate;an insulator layer over the substrate, the insulator layer having an opening to the substrate; anda cubic semiconductor material in the opening of the insulator layer and adjoining the substrate, the cubic semiconductor material extending over a top surface of insulator layer from a sidewall of the opening to a lateral distance, the cubic semiconductor material extending from the top surface of the insulator to a height, the lateral distance being greater than the height. 2. The semiconductor structure of claim 1, wherein the substrate comprises silicon. 3. The semiconductor structure of claim 1, wherein the cubic semiconductor material comprises a material selected from the group consisting essentially of germanium, a III-V compound, or a combination thereof. 4. The semiconductor structure of claim 1, wherein the cubic semiconductor material is lattice-mismatched to the substrate. 5. The semiconductor structure of claim 1, wherein dislocations in the cubic semiconductor material are trapped in the opening of the insulator layer. 6. The semiconductor structure of claim 1 further comprising an additional semiconductor layer over the cubic semiconductor material, the additional semiconductor layer comprising a p-n junction. 7. The semiconductor structure of claim 1, wherein the cubic semiconductor material comprises a first portion adjoining the substrate and a second portion distal from the substrate, the first portion comprising a first impurity, and the second portion comprising a second impurity, the first impurity capable of causing the first portion to grow with a vertical growth rate greater than a lateral growth rate, and the second impurity capable of causing the second portion to grow with a lateral growth rate greater than a vertical growth rate. 8. The semiconductor structure of claim 1 further comprising an additional semiconductor layer over the semiconductor material, the additional semiconductor layer coalescing over the insulator layer. 9. The semiconductor structure of claim 1 further comprising: a first active layer over the semiconductor material, the first active layer having a first band gap energy;a second active layer over the first active layer, the second active layer having a second band gap energy less than the first band gap energy; anda third active layer over the second active layer, the third active layer having a third band gap energy less than the second band gap energy. 10. The semiconductor structure of claim 9 further comprising a handle substrate bonded to the third active layer. 11. The semiconductor structure of claim 1 further comprising a solar cell over the semiconductor material. 12. A semiconductor structure comprising: a (110)-surface crystalline substrate;a dielectric layer over the crystalline substrate, the dielectric layer having a trench exposing a portion of the crystalline substrate; anda cubic semiconductor material in the trench of the dielectric layer and adjoining the crystalline substrate, the cubic semiconductor material being lattice mismatched to the crystalline substrate, the cubic semiconductor material extending over a top surface of dielectric layer from a sidewall of the trench to a lateral distance, the cubic semiconductor material extending from the top surface of the dielectric to a height, the lateral distance being greater than the height. 13. The semiconductor structure of claim 12, wherein the cubic semiconductor material comprises a material selected from the group consisting essentially of germanium, a III-V compound, or a combination thereof. 14. The semiconductor structure of claim 12, wherein dislocations in the cubic semiconductor material are trapped in the trench of the dielectric layer. 15. The semiconductor structure of claim 12, wherein the cubic semiconductor material comprises a first portion adjoining the substrate and a second portion distal from the substrate, the first portion comprising a first impurity, and the second portion comprising a second impurity, the first impurity capable of causing the first portion to grow with a vertical growth rate greater than a lateral growth rate, and the second impurity capable of causing the second portion to grow with a lateral growth rate greater than a vertical growth rate. 16. The semiconductor structure of claim 12 further comprising an additional semiconductor layer over the semiconductor material, the additional semiconductor layer coalescing over the dielectric layer.
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