IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0533482
(2006-09-20)
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등록번호 |
US-8386550
(2013-02-26)
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발명자
/ 주소 |
- Mauer, Volker
- Demirsoy, Suleyman Sirri
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출원인 / 주소 |
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인용정보 |
피인용 횟수 :
8 인용 특허 :
291 |
초록
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A hybrid FIR filter includes a plurality of FIR filter units arranged as Direct Form FIR filters, connected together in an arrangement similar to a Transpose Form FIR filter. The hybrid filter arrangement may be used to configure a larger FIR filter in a programmable logic device having one or more
A hybrid FIR filter includes a plurality of FIR filter units arranged as Direct Form FIR filters, connected together in an arrangement similar to a Transpose Form FIR filter. The hybrid filter arrangement may be used to configure a larger FIR filter in a programmable logic device having one or more specialized functional blocks, incorporating multipliers and adders, that are particularly well-suited for configuration as small Direct Form FIR filters.
대표청구항
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1. A programmable logic device configured as hybrid finite impulse response (FIR) filter circuitry; wherein: said programmable logic device has a plurality of specialized processing blocks each of which includes a plurality of multipliers and a single adder for simultaneously adding outputs of said
1. A programmable logic device configured as hybrid finite impulse response (FIR) filter circuitry; wherein: said programmable logic device has a plurality of specialized processing blocks each of which includes a plurality of multipliers and a single adder for simultaneously adding outputs of said multipliers; andsaid hybrid FIR filter circuitry comprises:a first number of said specialized processing blocks each of which is configured as a respective Direct Form FIR filter circuit in which each respective multiplier in said plurality of multipliers multiplies a respective sample by a respective coefficient and outputs of said respective multipliers are added simultaneously by said single adder to generate a Direct Form FIR output, said hybrid FIR filter circuitry having a second number of taps, each said Direct Form FIR filter circuit comprising a third number of taps, and said second number being a product of said first number and said third number;an adder chain comprising a plurality of additional adders, separate from any adder in said first number of said specialized processing blocks that adds said outputs of said respective multipliers, each of said additional adders having, as one input, one output of one of said respective Direct Form FIR filter circuits, and each of said additional adders other than a first of said additional adders having as one input an output of another one of said additional adders, said adder chain further comprising a respective output delay between (a) each said output of another one of said additional adders, that is an input to one of said additional adders other than a first one of said additional adders, and (b) said one of said additional adders other than a first one of said additional adders, andan input sample chain comprising a number of registers equal to said third number; wherein:each said register provides a sample substantially simultaneously to a corresponding input of each said Direct Form FIR filter circuit,said input sample chain shifts once at every clock cycle,each Direct Form FIR filter circuit generates an output at every said clock cycle, andeach said respective output delay has a delay period of a number of said clock cycles equal to said third number. 2. The programmable logic device of claim 1 wherein: each said Direct Form FIR filter circuit comprises a number of multiplier circuits equal to said third number; andeach said corresponding input comprises an input to a respective one of said multiplier circuits in each said Direct Form FIR filter circuit. 3. The programmable logic device of claim 2; wherein: said hybrid FIR filter circuitry further comprises a number of coefficients equal to said second number;said coefficients are divided into a number of groups equal to said first number;each said group comprises a number of coefficients equal to said third number; andeach coefficient in each said group is input to a respective one of said multiplier circuits. 4. The programmable logic device of claim 1 wherein: each said Direct Form FIR filter circuit comprises a number of multiplier circuits equal to said third number;said hybrid FIR filter circuitry further comprises a number of coefficients equal to said second number;said coefficients are divided into a number of groups equal to said first number;each said group comprises a number of coefficients equal to said third number; andeach coefficient in each said group is input to a respective one of said multiplier circuits. 5. A method of programmably configuring a programmable logic device as a hybrid finite impulse response (FIR) filter, said programmable logic device having a plurality of specialized processing blocks each of which includes a plurality of multipliers and a single adder for simultaneously adding outputs of said multipliers, said method comprising: programmably configuring each of a first number of said specialized processing blocks as a respective Direct Form FIR filter in which each respective multiplier in said plurality of multipliers multiplies a respective sample by a respective coefficient and outputs of said respective multipliers are added simultaneously by said single adder to generate a Direct Form FIR output, said hybrid FIR filter having a second number of taps, each said respective Direct Form FIR filter comprising a third number of taps, and said second number being a product of said first number and said third number;programmably configuring an adder chain from a plurality of additional adders, separate from any adder in said first number of said specialized processing blocks that adds said outputs of said respective multipliers, to add outputs of said Direct Form FIR filters, said adder chain comprising a respective delay preceding each of said additional adders in said adder chain, other than a first one of said additional adders in said adder chain, that has, as an input, one of said outputs of said Direct Form FIR filters;programmably configuring each said respective delay to have a delay period of a number of clock cycles equal to said third number; andprogrammably configuring an input sample chain comprising a number of registers equal to said third number; wherein:each said register provides a sample substantially simultaneously to a corresponding input of each said Direct Form FIR filter,said input sample chain shifts once at every clock cycle,each Direct Form FIR filter circuit generates an output at every said clock cycle, andsaid programmable logic device is configured as a hybrid FIR filter having a number of hybrid stages equal to said first number, each of said hybrid stages comprising a respective one of said Direct Form FIR filters. 6. The method of claim 5 wherein: each said Direct Form FIR filter comprises a number of multipliers equal to said third number; andeach said corresponding input comprises an input to a respective one of said multipliers in each said Direct Form FIR filter. 7. The method of claim 6 wherein said hybrid FIR filter comprises a number of coefficients equal to said second number; said method further comprising: programmably configuring a number of coefficient memories equal to said first number, each said coefficient memory storing a number of coefficients equal to said third number; andprogrammably configuring each coefficient stored in each said memory as an input to a respective one of said multipliers. 8. The method of claim 5 wherein: said programmably configuring each of a first number of said specialized processing blocks as a respective Direct Form FIR filter comprises programmably configuring each said Direct Form FIR filter to have a number of multipliers equal to said third number; andsaid hybrid FIR filter further comprises a number of coefficients equal to said second number; said method further comprising:programmably configuring a number of coefficient memories equal to said first number, each said coefficient memory storing a number of coefficients equal to said third number; andprogrammably configuring each coefficient stored in each said memory as an input to a respective one of said multipliers. 9. A non-transitory data storage medium encoded with non-transitory machine-executable instructions for performing a method of programmably configuring a programmable logic device as a hybrid finite impulse response (FIR) filter, said programmable logic device having a plurality of specialized processing blocks each of which includes a plurality of multipliers and a single adder for simultaneously adding outputs of said multipliers, said instructions comprising: instructions to programmably configure each of a first number of said specialized processing blocks as a respective Direct Form FIR filter in which each respective multiplier in said plurality of multipliers multiplies a respective sample by a respective coefficient and outputs of said respective multipliers are added simultaneously by said single adder to generate a Direct Form FIR output, said hybrid FIR filter having a second number of taps, said instructions to programmably configure each of said first number of said specialized processing blocks as said respective Direct Form FIR filter comprises instructions to programmably configure each said Direct Form FIR filter with a third number of taps, said second number being a product of said first number and said third number;instructions to programmably configure an adder chain from a plurality of additional adders, separate from any adder in said first number of said specialized processing blocks that adds said outputs of said respective multipliers, to add outputs of said Direct Form FIR filters, said adder chain comprising a respective delay preceding each of said additional adders in said adder chain, other than a first one of said additional adders in said adder chain, that has as an input one of said Direct Form FIR filters;instructions to programmably configure each said respective delay to have a delay period of a number of clock cycles equal to said third number; andinstructions to programmably configure an input sample chain comprising a number of registers equal to said third number; wherein:each said register provides a sample substantially simultaneously to a corresponding input of each said Direct Form FIR filter,said input sample chain shifts once at every clock cycle,each Direct Form FIR filter circuit generates an output at every said clock cycle, andsaid programmable logic device is configured as a hybrid FIR filter having a number of hybrid stages equal to said first number, each of said hybrid stages comprising a respective one of said Direct Form FIR filters. 10. The non-transitory data storage medium of claim 9 wherein said instructions further comprise: instructions to configure each said Direct Form FIR filter with a number of multipliers equal to said third number; wherein:each said corresponding input comprises an input to a respective one of said multipliers in each said Direct Form FIR filter. 11. The non-transitory data storage medium of claim 10 wherein said hybrid FIR filter comprises a number of coefficients equal to said second number; said instructions further comprising: instructions to programmably configure a number of coefficient memories equal to said first number, each said coefficient memory storing a number of coefficients equal to said third number; andinstructions to programmably configure each coefficient stored in each said memory as an input to a respective one of said multipliers. 12. The non-transitory data storage medium of claim 9 wherein: said instructions to programmably configure each of a first number of said specialized processing blocks as a respective Direct Form FIR filter comprise instructions to programmably configure each said Direct Form FIR filter to have a number of multipliers equal to said third number; andsaid hybrid FIR filter further comprises a number of coefficients equal to said second number; said instructions further comprising:instructions to programmably configure a number of coefficient memories equal to said first number, each said coefficient memory storing a number of coefficients equal to said third number; andinstructions to programmably configure each coefficient stored in each said memory as an input to a respective one of said multipliers.
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