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Fabrication method and fabrication apparatus of group III nitride crystal substance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
출원번호 US-0949268 (2010-11-18)
등록번호 US-8404569 (2013-03-26)
우선권정보 JP-2005-379917 (2005-12-28); JP-2006-218475 (2006-08-10)
발명자 / 주소
  • Kasai, Hitoshi
  • Okahisa, Takuji
  • Fujita, Shunsuke
  • Matsumoto, Naoki
  • Ijiri, Hideyuki
  • Sato, Fumitaka
  • Motoki, Kensaku
  • Nakahata, Seiji
  • Uematsu, Koji
  • Hirota, Ryu
출원인 / 주소
  • Sumitomo Electric Industries, Ltd.
대리인 / 주소
    McDermott Will & Emery LLP
인용정보 피인용 횟수 : 1  인용 특허 : 31

초록

A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of

대표청구항

1. A fabrication method of a group III nitride crystal substance, the method comprising steps of: cleaning an interior of a reaction chamber by introducing HCl gas into said reaction chamber, andvapor deposition of a group III nitride crystal substance having Si atoms doped in said cleaned reaction

이 특허에 인용된 특허 (31)

  1. Tang, Sang Dang, Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices.
  2. Tang,Sang Dang, Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices.
  3. Kasai, Hitoshi; Okahisa, Takuji; Fujita, Shunsuke; Matsumoto, Naoki; Ijiri, Hideyuki; Sato, Fumitaka; Motoki, Kensaku; Nakahata, Seiji; Uematsu, Koji; Hirota, Ryu, Fabrication method and fabrication apparatus of group III nitride crystal substance.
  4. Kasai, Hitoshi; Okahisa, Takuji; Fujita, Shunsuke; Matsumoto, Naoki; Ijiri, Hideyuki; Sato, Fumitaka; Motoki, Kensaku; Nakahata, Seiji; Uematsu, Koji; Hirota, Ryu, Fabrication method and fabrication apparatus of group III nitride crystal substance.
  5. Belyansky, Michael P.; Chidambarrao, Dureseti; Clevenger, Lawrence A.; Kumar, Kaushik A.; Radens, Carl, Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same.
  6. Vaudo Robert P. ; Redwing Joan M. ; Tischler Michael A. ; Brown Duncan W., GaN-based devices using (Ga, AL, In)N base layers.
  7. Vaudo, Robert P.; Redwing, Joan M.; Tischler, Michael A.; Brown, Duncan W.; Flynn, Jeffrey S., GaN-based devices using thick (Ga, Al, In)N base layers.
  8. Tsuda, Einosuke, Gas exhaust system of film-forming apparatus, film-forming apparatus, and method for processing exhaust gas.
  9. Vaudo, Robert P.; Flynn, Jeffrey S.; Brandes, George R.; Redwing, Joan M.; Tischler, Michael A., III-V nitride substrate boule and method of making and using the same.
  10. Vaudo, Robert P.; Flynn, Jeffrey S.; Brandes, George R.; Redwing, Joan M.; Tischler, Michael A., III-V nitride substrate boule and method of making and using the same.
  11. Park, Sung-Joon; Kim, Seong-Goo, Integrated circuits including insulating spacers that extend beneath a conductive line.
  12. Park,Sung Joon; Kim,Seong Goo, Integrated circuits including spacers that extend beneath a conductive line.
  13. Drynan, John M., Interconnect line selectively isolated from an underlying contact plug.
  14. Drynan, John M., Interconnect line selectively isolated from an underlying contact plug.
  15. Drynan, John M., Interconnect line selectively isolated from an underlying contact plug.
  16. Drynan, John M., Interconnect line selectively isolated from an underlying contact plug.
  17. Drynan,John M., Interconnect line selectively isolated from an underlying contact plug.
  18. Lee, Yoon Jik; Kim, Jeong Tae, Method for fabricating cell plugs of semiconductor device.
  19. Hong Chang-Hee,KRX ; Kim Sun Tae,KRX, Method for forming GaN semiconductor single crystal substrate and GaN diode with the substrate.
  20. J. Anthony Powell ; Philip G. Neudeck, Method for growing low-defect single crystal heteroepitaxial films.
  21. Powell J. Anthony ; Larkin David J. ; Neudeck Philip G. ; Matus Lawrence G., Method for growth of crystal surfaces and growth of heteroepitaxial single crystal films thereon.
  22. Nishio, Johji; Ishikawa, Masayuki, Method for preparing epitaxial-substrate and method for manufacturing semiconductor device employing the same.
  23. Sakuma, Takeshi, Method of cleaning processing chamber of semiconductor processing apparatus.
  24. Park, Je-Min; Son, Seung-young; Hwang, Yoo-Sang, Method of manufacturing semiconductor device with interconnections and interconnection contacts and a device formed thereby.
  25. Ueda Tetsuzo ; Solomon Glenn S. ; Miller David J., Particle trap apparatus and methods.
  26. Molnar Richard J., Process for producing high-quality III-V nitride substrates.
  27. Hardwick, Steven; McManus, James V., Process for sorption of hazardous waste products from exhaust gas streams.
  28. Lee, Yoon Jik; Kim, Jeong Tae, Semiconductor device having cell plugs.
  29. Taniyama, Tomoshi; Takashima, Yoshikazu; Ohno, Mikio, Semiconductor device manufacturing apparatus and manufacturing method of semiconductor device.
  30. Komatsu,Tomohito, Trapping device, processing system, and method removing impurities.
  31. Jacob Guy M. (Creteil FRX) Hallais Jean P. (Ablon FRX), Vapor deposition of single crystal gallium nitride.

이 특허를 인용한 특허 (1)

  1. Shibata, Masatomo; Yoshida, Takehiro; Kitamura, Toshio; Abe, Yukio, Semiconductor substrate manufacturing method.
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