IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0590991
(2012-08-21)
|
등록번호 |
US-8405191
(2013-03-26)
|
발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
1 인용 특허 :
61 |
초록
▼
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation l
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.
대표청구항
▼
1. A semiconductor device comprising: a substrate having a first surface and a second, opposing surface;a first conductive pad disposed on the first surface;a second conductive pad disposed on the first surface;a plurality of through-wafer interconnect (TWI) structures including a first TWI structur
1. A semiconductor device comprising: a substrate having a first surface and a second, opposing surface;a first conductive pad disposed on the first surface;a second conductive pad disposed on the first surface;a plurality of through-wafer interconnect (TWI) structures including a first TWI structure extending through and electrically connected with the first conductive pad and a second TWI structure extending through and electrically insulated from the second conductive pad. 2. The semiconductor device of claim 1, wherein the substrate comprises a semiconductor material selected from the group consisting of silicon, gallium arsenide, indium phosphide, polysilicon, silicon-on-ceramic, silicon-on-glass, silicon-on-sapphire, and combinations of any thereof. 3. The semiconductor device of claim 1, further comprising a passivation material over the first surface of the substrate. 4. The semiconductor device of claim 3, wherein the passivation material comprises a material selected from the group consisting of silicon oxide, silicon nitride, phosphosilicate glass (PSG), borosilicate glass (BSG), and an organic polymeric material. 5. The semiconductor device of claim 4, further comprising dielectric material between the passivation material and the first surface of the substrate and under the first conductive pad and the second conductive pad. 6. The semiconductor device of claim 5, wherein the dielectric material comprises borophosphosilicate glass, a silicon oxide, or silicon nitride. 7. The semiconductor device of claim 1, wherein the first TWI structure includes: an insulative material over a surface of a first aperture between the first surface and the second, opposing surface;at least one conductive layer over the insulative material over the surface of the first aperture and at least partially over and in electrical communication with the first conductive pad; anda conductive material filling the first aperture. 8. The semiconductor device of clam 7, wherein the insulative material over the surface of the first aperture is selected from the group consisting of LSO, a PARYLENE™ polymer, silicon dioxide, aluminum oxide, TEOS, polybenzoxazole (PBO), benzocyclobutene (BCB) and combinations of any of the foregoing. 9. The semiconductor device of claim 7, wherein the second TWI structure includes: insulative material over a surface of a second aperture extending between the first surface and the second, opposing surface;at least one conductive layer over the insulative material over the surface of the second aperture and electrically insulated from the second conductive pad; anda conductive material filling the second aperture. 10. The semiconductor device of clam 9, wherein the insulative material over the surface of the first aperture is selected from the group consisting of LSO, a PARYLENE™ polymer, silicon dioxide, aluminum oxide, TEOS, polybenzoxazole (PBO), benzocyclobutene (BCB) and combinations of any of the foregoing. 11. The semiconductor device of claim 9, wherein the conductive material in the first aperture and the conductive material in the second aperture are exposed through the second, opposing surface in the substrate. 12. The semiconductor device of claim 11, wherein the at least one conductive layer over the surface of the first aperture and the at least one conductive layer over the surface of the second aperture each comprises a seed layer. 13. The semiconductor device of claim 12, wherein the seed layer is selected from the group consisting of tungsten (W), tantalum (Ta), copper (Cu), nickel (Ni and titanium nitride (TiN). 14. The semiconductor device of claim 12, wherein the at least one conductive layer over the surface of the first aperture and the at least one conductive layer over the surface of the second aperture each further comprises a solder-wettable material layer. 15. The semiconductor device of claim 14, wherein the solder-wettable material comprises nickel. 16. The semiconductor device of claim 15, wherein the conductive material filling the first aperture and the second aperture comprises a solder. 17. The semiconductor device of claim 9, wherein the conductive material filling the first aperture and the conductive material filling the second aperture is selected from the group consisting of a metal, an alloy other than a solder, a solder alloy, a solder paste, a conductive epoxy and a conductor-filled epoxy. 18. The semiconductor device of claim 9, wherein the at least one conductive layer of the first aperture and the at least one conductive layer of the second aperture are selected from the group consisting of titanium (Ti), polysilicon (Si), palladium (Pd), tin (Sn), tantalum (Ta), tungsten (W), cobalt (Co), copper (Cu), silver (Ag), aluminum (Al), iridium (Ir), gold (Au), molybdenum (Mo), platinum (Pt), nickel-phosphorus (NiP), palladium-phosphorus (Pd—P), cobalt-phosphorus (Co—P), a cobalt-tungsten-phosphorous (Co—W—P) alloy, other alloys of any of the foregoing metals, a conductive polymer or conductive material entrained in a polymer and mixtures of any thereof. 19. The semiconductor device of claim 11, further comprising discrete external conductive elements operably coupled to the first TWI structure and the second TWI structure on at least one of the first surface and the second, opposing surface. 20. The semiconductor device of claim 19, wherein discrete external conductive elements are operably coupled to the first TWI structure and the second TWI structure on each of the first surface and the second, opposing surface.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.