[특허]Circuit and method

Circuit and method 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H04B-001/02
출원번호	US-0954872 (2010-11-28)
등록번호	US-8406705 (2013-03-26)
발명자 / 주소	Boos, Zdravko
출원인 / 주소	Intel Mobile Communications GmbH
대리인 / 주소	SpryIP, LLC
인용정보	피인용 횟수 : 0 인용 특허 : 27

초록

Implementations related to circuits including an oscillator and a switch-mode DC/DC converter are presented herein.

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1. A circuit, comprising: an oscillator configured to provide a first signal having a first frequency;a frequency converter coupled to the oscillator, and configured to convert the first signal to a second signal having a second frequency equal to a sum of the first frequency and an offset frequency; anda switch-mode DC/DC converter coupled to the frequency converter, and configured to convert a first voltage to a second voltage, wherein the DC/DC converter is controlled by the second signal. 2. The circuit of claim 1, wherein a switching frequency of the DC/DC converter is controlled by the second signal. 3. The circuit of claim 1, wherein the second frequency is locked to the first frequency. 4. The circuit of claim 1, wherein the oscillator comprises a voltage-controlled or digitally controlled oscillator. 5. The circuit of claim 1, wherein the oscillator and the DC/DC converter are integrated in the same integrated circuit. 6. A receiver circuit, comprising: a frequency synthesizer to provide a first signal having a first frequency;a down-conversion mixer coupled to the frequency synthesizer, and configured to mix a received signal with the first signal;a frequency converter coupled to the frequency synthesizer, and configured to convert the first signal to a second signal having a second frequency; anda switch-mode DC/DC converter coupled to the frequency converter and integrated in a common integrated circuit therewith, and configured to convert a first voltage to a second voltage, wherein the DC/DC converter is controlled by the second signal. 7. The receiver circuit of claim 6, wherein the second frequency is locked to the first frequency. 8. The receiver circuit of claim 6, wherein the frequency synthesizer and the DC/DC converter are integrated in the same integrated circuit. 9. The receiver circuit of claim 6, wherein the second frequency is M/N times the first frequency, M and N are integers, and wherein M≠N. 10. The receiver circuit of claim 6, wherein the frequency synthesizer comprises a voltage-controlled oscillator or a digitally controlled oscillator. 11. The receiver circuit of claim 6, wherein the first signal has a first frequency bandwidth and the second signal has a second frequency bandwidth, and wherein the first and second frequency bandwidths do not overlap. 12. The receiver circuit of claim 6, wherein the DC/DC converter is self-oscillating. 13. A transceiver circuit, comprising: a first frequency synthesizer configured to provide a first signal having a first frequency;an up-conversion mixer coupled to the first frequency synthesizer, and configured to mix a signal to be transmitted with the first signal;a second frequency synthesizer configured to provide a second signal having a second frequency;a down-conversion mixer coupled to the second frequency synthesizer, and configured to mix a received signal with the second signal;a first frequency converter coupled to the first frequency synthesizer, and configured to convert the first signal to a third signal having a third frequency; anda first switch-mode DC/DC converter coupled to the first frequency converter, and configured to convert a first voltage to a second voltage, wherein the first DC/DC converter is controlled by the third signal. 14. The transceiver of claim 13, further comprising: a second frequency converter coupled to the second frequency synthesizer, and configured to convert the second signal to a fourth signal having a fourth frequency; anda second switch-mode DC/DC converter coupled to the second frequency converter, and configured to convert a third voltage to a fourth voltage, wherein the second DC/DC converter is controlled by the fourth signal. 15. The transceiver circuit of claim 13, wherein the first and second frequency synthesizers and the first and second DC/DC converters are integrated in the same integrated circuit. 16. A method comprising: providing a first signal having a first frequency;down-converting a received signal by mixing it with the first signal;converting the first signal to a second signal having a second frequency equal to a sum of the first frequency and an offset frequency; andconverting a first DC voltage to a second DC voltage, wherein the voltage conversion is controlled by the second signal. 17. The method of claim 16, wherein the second frequency is locked to the first frequency. 18. The method of claim 16, wherein the second frequency is M/N times the first frequency, M and N are integers, and wherein M≠N.

이 특허에 인용된 특허 (27)

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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