최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0497655 (2009-07-04) |
등록번호 | US-8410617 (2013-04-02) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 14 인용 특허 : 282 |
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS mem
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
1. An integrated circuit structure comprising: a first substrate comprising a first surface having interconnect contacts;a second substrate comprising a first surface having interconnect contacts; anda bond layer between the first surface of the first substrate and the first surface of the second su
1. An integrated circuit structure comprising: a first substrate comprising a first surface having interconnect contacts;a second substrate comprising a first surface having interconnect contacts; anda bond layer between the first surface of the first substrate and the first surface of the second substrate, comprising: a plurality of bonds formed from the interconnect contacts of the first surfaces of the first and second substrates and forming portions of signal paths between the first surface of the second substrate and the first surface of the first substrate; and,at least one bond formed between the first surfaces of the first and second substrates and not forming portions of a signal path between the first surfaces of the first and second substrates, wherein at least one of the first substrate and second substrate is substantially flexible and at least one of the first substrate and the second substrate is and formed from a semiconductor wafer or portion thereof; andat least one conductive path that passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said at least one of said first and second substrates, wherein the insulation material comprises a low stress dielectric material having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon. 2. The structure of claim 1, wherein the second substrate is one of a thinned monocrystalline semiconductor substrate and a thinned polycrystalline semiconductor substrate. 3. The structure of claim 1, wherein circuitry is formed on the second substrate comprising one of active circuitry and passive circuitry. 4. The structure of claim 1, wherein circuitry is formed on the second substrate comprising both active circuitry and passive circuitry. 5. The structure of claim 1, wherein the first substrate is a substrate having circuitry formed thereon. 6. The structure of claim 5, wherein the circuitry of the first substrate is one of active circuitry and passive circuitry. 7. The structure of claim 5, wherein the circuitry of the first substrate comprises both active circuitry and passive circuitry. 8. The structure of claim 1, further comprising: at least one additional thinned substrate having circuitry formed thereon;a first of said at least one additional thinned substrate being bonded to the second substrate and any additional thinned substrates being bonded to the directly adjacent additional thinned substrate; andconductive paths formed between said first of said at least one additional thinned substrate and at least one of said first and second substrates and also between each additional thinned substrate and at least one of said substrates of the integrated circuit structure. 9. The structure of claim 8, wherein at least two of the first, the second and the at least one additional thinned substrates are formed using a different process technology, wherein the different process technology is selected from the group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance. 10. The structure of claim 8, wherein at least one of the first, the second and the at least one additional thinned substrates comprises a microprocessor. 11. The structure of claim 8, wherein: at least one substrate of the first, the second and the at least one additional thinned substrates has memory circuitry formed thereon; andat least one substrate of the first, the second and the at least one additional thinned substrates has logic circuitry formed thereon that performs tests on the at least one substrate that has memory circuitry formed thereon. 12. The structure of claim 8, wherein at least one substrate of the first, the second and the at least one additional thinned substrates has memory circuitry formed thereon, the memory circuitry having a plurality of memory locations, wherein at least one memory location of the plurality of memory locations is used for sparing and wherein data from the at least one memory location on the at least one substrate having memory circuitry formed thereon is used instead of data from a defective memory location on the at least one substrate that has memory circuitry formed thereon. 13. The structure of claim 8, wherein: at least one substrate of the first, the second and the at least one additional thinned substrates has memory circuitry formed thereon; andat least one substrate of the first, the second and the at least one additional thinned substrates has logic circuitry formed thereon that performs programmable gate line address assignment with respect to the at least one substrate having memory circuitry formed thereon. 14. The structure of claim 8, further comprising a plurality of interior vertical interconnections that traverse at least one of the first, the second and the at least one additional thinned substrates. 15. The structure of claim 8, wherein information processing is performed on data routed between the circuitry of at least two of the first, the second and the at least one additional thinned substrates. 16. The structure of claim 8, wherein at least one of the first, the second and the at least one additional thinned substrates has reconfiguration circuitry. 17. The structure of claim 8, wherein at least one of the first, the second, and the at least one additional thinned substrates has logic circuitry formed thereon for performing at least one function from the group consisting of: virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing. 18. The structure of claim 8, further comprising: a memory array having a plurality of memory storage cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell stores a data value and has circuitry for coupling the data value to one of the plurality of data lines in response to receiving a gate control signal from one of the plurality of gate lines;circuitry that generates the gate control signal in response to receiving an address, including means for mapping addresses to gate lines; anda controller that determines if one of the plurality of memory cells is defective and alters said mapping to remove references to the one of the plurality of memory cells that is defective. 19. The structure of claim 8, further comprising: at least one controller substrate having logic circuitry formed thereon;at least one memory substrate having memory circuitry formed thereon;a plurality of data lines and a plurality of gate lines on each memory substrate;an array of memory cells on each memory substrate, each memory cell stores a data value and has circuitry that couples the data value to one of the plurality of data lines in response to selecting one of the plurality of gate lines;a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit has programmable gates to receive address assignments for at least one gate line of the plurality of gate lines and wherein the address assignments for determining which of the plurality of gate lines is selected for each programmed address assignment; andcontroller substrate logic that determines if one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines. 20. The structure of claim 19, wherein the controller substrate logic: tests the array of memory cells periodically to determine if one of the array of memory cells is defective; andremoves references in the address assignments to gate lines that cause detected defective memory cells to couple data values to the plurality of data lines. 21. The structure of claim 19, further comprising: programmable logic to prevent the use of data values from the plurality of data lines when gate lines cause detected defective memory cells to couple data values to the plurality of data lines. 22. The structure of claim 19, wherein the array of memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order and wherein the physical order of at least one memory cell is different than the logical order of the at least one memory cell. 23. The structure of claim 19, wherein: the logic circuitry of the at least one controller substrate is tested by an external means; andthe array of memory cells of the at least one memory substrate are tested by the logic circuitry of the at least one controller substrate, wherein the testing achieves a functional testing of a substantial portion of the array of memory cells. 24. The structure of claim 19, wherein the logic circuitry of the at least one controller substrate performs functional testing of a substantial portion of the array of memory cells. 25. The structure of claim 19, wherein the controller substrate logic is further configured to: prevent the use of at least one defective gate line; andreplace references to memory cells addressed using the defective gate line with references to spare memory cells addressed using a spare gate line. 26. The structure of claim 19, wherein the controller substrate logic is further configured to prevent the use of at least one defective gate line. 27. The structure of claim 19, wherein the logic circuitry of the at least one controller substrate can perform all functional testing of the array of memory cells of the at least one memory substrate. 28. The structure of claim 1, wherein the first substrate is a non-semiconductor material. 29. The structure of claim 1, wherein the second substrate is thinned to about 50 microns or less. 30. The structure of claim 1, wherein the first substrate and the second substrate are the same size or overlap each other completely. 31. The integrated circuit structure of claim 1, wherein at least one of the first and second substrates is at least one of the following: less than about 10 microns in thickness; comprises a dielectric layer with a stress of about 5×108 dynes/cm2 or less; comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible. 32. The structure of claim 1, wherein each of the first substrate and the second substrate comprises said first surface thereof and a second surface thereof, said second surface thereof being opposite to said first surface thereof, wherein at least one of the first and second substrates is a thinned substrate, and wherein the second surface of said thinned substrate is polished surface to make the substrate substantially flexible. 33. The structure of claim 1, wherein at least two of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less, wherein the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate, wherein the insulation material comprises a low stress dielectric having a stress of 5×108 dynes/cm 2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 34. The structure of claim 1, wherein at least three of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less, wherein the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate, wherein the insulation material comprises a low stress dielectric having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 35. The structure of claim 1, wherein at least four of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less, wherein the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate, the insulation material comprises a low stress dielectric having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 36. An integrated circuit structure comprising: a first substrate having topside and bottomside surfaces, wherein the topside surface of the first substrate has interconnect contacts;a second substrate having topside and bottomside surfaces, wherein the bottomside surface of the second substrate has interconnect contacts; anda bond layer between the topside surface of the first substrate and the bottomside surface of the second substrates, comprising:a plurality of bonds formed from the interconnect contacts forming conductive paths between the topside of the first substrate and the bottomside of the second substrate; and,at least one bond formed between the topside of the first substrate and the bottomside of the second substrate forming at least one: of a non-conductive contact; and a conductive contact not formed from one of said interconnect contacts;wherein at least one of the first substrate and the second substrate is substantially flexible and at least one of the first and second substrates is and formed from a semiconductor wafer or portion therof; andat least one conductive path that passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said at least one of said first and second substrates, wherein the insulation material comprises a low stress dielectric material having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon. 37. The integrated circuit structure of claim 36, wherein selected ones of said interconnect contacts of said topside surface of said first substrate are in electrical contact with selected ones of the interconnect contacts of said bottomside surface of said second substrate so as to form said electrical connections. 38. The structure of claim 36, further comprising: at least one additional thinned substrate having circuitry formed thereon;a first of said at least one additional thinned substrate being bonded to the second substrate and any additional thinned substrates being bonded to the directly adjacent additional thinned substrate; andconductive paths formed between said first of said at least one additional thinned substrate and at least one of said first and second substrates and also between each additional thinned substrate and at least one of said substrates of the integrated circuit structure. 39. The structure of claim 38, further comprising: at least one controller substrate having logic circuitry formed thereon;at least one memory substrate having memory circuitry formed thereon;a plurality of data lines and a plurality of gate lines on each memory substrate;an array of memory cells on each memory substrate, each memory cell stores a data value and has circuitry that couples the data value to one of the plurality of data lines in response to selecting one of the plurality of gate lines;a gate line selection circuit that enables a gate line for a memory operation, wherein the gate line selection circuit has programmable gates to receive address assignments for at least one gate line of the plurality of gate lines and wherein the address assignments for determining which of the plurality of gate lines is selected for each programmed address assignment; andcontroller substrate logic that determines if one memory cell of the array of memory cells is defective and alters the address assignments of the plurality of gate lines to remove references to the gate line that causes the defective memory cell to couple a data value to one of the plurality of data lines. 40. The structure of claim 39, wherein the controller substrate logic: tests the array of memory cells periodically to determine if one of the array of memory cells is defective; andremoves references in the address assignments to gate lines that cause detected defective memory cells to couple data values to the plurality of data lines. 41. The structure of claim 39, further comprising: programmable logic to prevent the use of data values from the plurality of data lines when gate lines cause detected defective memory cells to couple data values to the plurality of data lines. 42. The structure of claim 39, wherein the array of memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order and wherein the physical order of at least one memory cell is different than the logical order of the at least one memory cell. 43. The structure of claim 39, wherein: the logic circuitry of the at least one controller substrate is tested by an external means; andthe array of memory cells of the at least one memory substrate are tested by the logic circuitry of the at least one controller substrate, wherein the testing achieves a functional testing of a substantial portion of the array of memory cells. 44. The structure of claim 39, wherein the logic circuitry of the at least one controller substrate performs functional testing of a substantial portion of the array of memory cells. 45. The structure of claim 39, wherein the controller substrate logic is further configured to: prevent the use of at least one defective gate line; andreplace references to memory cells addressed using the defective gate line with references to spare memory cells addressed using a spare gate line. 46. The structure of claim 39, wherein the controller substrate logic is further configured to prevent the use of at least one defective gate line. 47. The structure of claim 39, wherein the logic circuitry of the at least one controller substrate can perform all functional testing of the array of memory cells of the at least one memory substrate. 48. The structure of claim 36, wherein the second substrate is thinned to about 50 microns or less. 49. The structure of claim 36, wherein the first substrate and the second substrate are the same size or overlap each other completely. 50. The integrated circuit structure of claim 36, wherein at least one of the first and second substrates is at least one of the following: less than about 10 microns in thickness; comprises a dielectric layer with a stress of about 5×108 dynes/cm2 or less; comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible. 51. The structure of claim 36, wherein the bottomside of the first substrate is polished to make the substrate substantially flexible. 52. The structure of claim 36, wherein at least two of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less; the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 53. The structure of claim 36, wherein at least three of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less; the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 54. The structure of claim 36, wherein at least four of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less; the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 55. An integrated circuit structure comprising: a first substrate having a first and second surface;a second substrate having a first and second surface, wherein said second surfaces of the first and second substrates are opposite to said first surfaces;a plurality of bonded contacts between the first surface of the first substrate and the first surface of the second substrate;wherein at least one of said contacts is a signal path conductive contact and at least another one of said contacts is one of: a signal path conductive contact; a non-signal path conductive contact; and a non-conductive contact;wherein at least one of the first substrate and second substrate is substantially flexible and at least one of the first substrate and the second substrate is and formed from a semiconductor wafer or portion thereof; andat least one conductive path that passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said at least one of said first and second substrates, wherein the insulation material comprises a low stress dielectric material having a stress of 5×108 dynes/cm2 or less, and wherein said low stress dielectric is at least one of an oxide of silicon and a nitride of silicon. 56. The structure of claim 55, wherein the second substrate is thinned to about 50 microns or less. 57. The structure of claim 55, wherein the first substrate and the second substrate are the same size or overlap each other completely. 58. The integrated circuit structure of claim 55, wherein at least one of the first and second substrates is at least one of the following: less than about 10 microns in thickness; and comprises a dielectric layer with a stress of about 5×108 dynes/cm2 or less; comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible. 59. The structure of claim 36, wherein at least one of the first and second substrates is a thinned substrate, and wherein the second surface of said thinned substrate is polished to make the substrate substantially flexible. 60. The structure of claim 55, wherein at least two of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less; the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 61. The structure of claim 55, wherein at least three of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5 ×108 dynes/cm2 or less; the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereon; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry. 62. The structure of claim 55, wherein at least four of: the first substrate is a non-semiconductor material; the second substrate comprises at least one dielectric layer with a stress of about 5×108 dynes/cm2 or less; the dielectric layer is at least one of silicon dioxide and an oxide of silicon; the second substrate has one of logic circuitry and memory circuitry formed thereonf; at least one conductive path passes vertically through at least one of the first and second substrates and is insulated by an insulation material from said substrate; at least one of the first and second substrates is a monocrystalline semiconductor substrate; at least one of said first and second substrates comprises memory refresh circuitry; at least one of said first and second substrates comprises test circuitry for testing circuitry on a different substrate; at least one of said first and second substrates comprises redundant vertical interconnections passing through said one of said first and second substrates; at least one of said substrates comprises reconfiguration circuitry; at least one of said first and second substrates comprises a front side having semiconductor devices formed thereon and a back side opposite said front side, wherein the back side is polished to make the substrate substantially flexible; at least one of the first and second substrates comprises ECC circuitry; at least one of the first and second substrates comprises indirect addressing circuitry; at least one of the first and second substrates comprises content addressing circuitry; at least one of the first and second substrates comprises data compression circuitry; at least one of the first and second substrates comprises data decompression circuitry; at least one of the first and second substrates comprises graphics acceleration circuitry; at least one of the first and second substrates comprises audio encoding circuitry; at least one of the first and second substrates comprises audio decoding circuitry; at least one of the first and second substrates comprises video encoding circuitry; at least one of the first and second substrates comprises video decoding circuitry; at least one of the first and second substrates comprises voice recognition circuitry; at least one of the first and second substrates comprises handwriting recognition circuitry; at least one of the first and second substrates comprises power management circuitry; at least one of the first and second substrates comprises database processing circuitry.
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