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Methods and circuits comprising a reliability measurement unit (RMU) for generating log-likelihood ratio (LLR) values corresponding to 1T for use in a soft output Viterbi algorithm (“SOVA”) decoder. The RMU operates with an nT clock signal. 1T signals generated by an add, compare, select circuit (AC

Methods and circuits comprising a reliability measurement unit (RMU) for generating log-likelihood ratio (LLR) values corresponding to 1T for use in a soft output Viterbi algorithm (“SOVA”) decoder. The RMU operates with an nT clock signal. 1T signals generated by an add, compare, select circuit (ACS) of the SOVA generates 1T decision data and a path equivalency detector generates 1T path equivalency information for 1T SOVA decoding and applies the 1T data to the RMU operating with an nT clock frequency (1/n'th that of the 1T clock signal). The nT RMU receives a plurality of 1T inputs on each nT clock signal pulse and generates 1T LLR information for use by the SOVA decoder. Other components of the SOVA may also operate using the nT clock signal pulse or may operate using a 1T clock signal.

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1. A method for generating 1T log-likelihood ratio (LLR) values from an nT reliability measurement unit (RMU) in a soft output Viterbi algorithm (SOVA) decoder where n is greater than 1, the method comprising: responsive to each nT clock pulse, performing the steps of:receiving multiple inputs in th

1. A method for generating 1T log-likelihood ratio (LLR) values from an nT reliability measurement unit (RMU) in a soft output Viterbi algorithm (SOVA) decoder where n is greater than 1, the method comprising: responsive to each nT clock pulse, performing the steps of:receiving multiple inputs in the RMU the multiple inputs corresponding to signals generated by 1T operation of the SOVA decoder;generating LLR values in the nT RMU based on the received 1T multiple inputs; andoutputting the LLR values as soft output information associated with the decision data output of the SOVA decoder. 2. The method of claim 1wherein the step of receiving further comprises:receiving state metric data (SMD) values from an add, compare, select (ACS) component of the SOVA decoder as a portion of the multiple inputs to the nT RMU component of the SOVA decoder where the n SMD values correspond to n sequential outputs of the ACS as though operating at a 1T clock frequency; andreceiving path equivalency information values from a path equivalency detector component of the SOVA decoder as a portion of the multiple inputs to the nT RMU component of the SOVA decoder where the path equivalency information values correspond to n sequential outputs of the path equivalency detector as though operating at a 1T clock frequency. 3. The method of claim 2where n is 2,where the nT RMU comprises a plurality of slices, each slice generating 2 LLR values to advance the LLR value computation to a next depth of a predetermined fixed depth,wherein the SMD values received at nT clock pulse number t are SMDt-1 and SMDt,wherein the path equivalency information values received at nT clock pulse number t are EQXt-1, EQYt, EQYt-1, and EQZt, andwherein the step of generating further comprises:generating 2 LLR values responsive to nT clock pulse number t as Yt and Zt as: if (EQYt=1) & (EQXt-1=1) then Yt=Wt-2 if (EQYt=1) & (EQXt-1=0) then Yt=min(Wt-2, SMDt-1)if (EQYt=0) & (EQXt-1=1) then Yt=min(Wt-2, SMDt)if (EQYt=0) & (EQXt-1=0) then Yt=min(Wt-2, SMDt-1, SMDt)if (EQZt=1) & (EQYt-1=1) then Zt=Xt-2 if (EQZt=1) & (EQYt-1=0) then Zt=min(Xt-2, SMDt-1)if (EQZt=0) & (EQYt-1=1) then Zt=min(Xt-2, SMDt)if (EQZt=0) & (EQYt-1=0) then Zt=min(Xt-2, SMDt-1, SMDt),where:min is a function that determines the minimum value of listed parameters,Wt-2 is an LLR value relating to a preceding nT clock signal pulse, andXt-2 is an LLR value relating to a preceding nT clock signal pulse. 4. The method of claim 3wherein the step of generating further comprises:generating final LLR values in conjunction with a final slice including Zt as above and Zt-1 as: if (EQZt-1=1) then Zt-1=min(Yt-2, SMDt-1)if (EQZt-1=0) then Zt-1=Yt-2. 5. The method of claim 3wherein the step of generating further comprises:applying initial LLR values representing highest confidence as Wt-2 and Xt-2 as inputs to a first slice. 6. A circuit usable in conjunction with a soft output Viterbi algorithm (SOVA) decoder, the SOVA decoder operable to generate 1T signals as inputs to the circuit, the circuit comprising: an nT clock signal source adapted to generate an nT clock signal pulse at a frequency of 1/n of the data rate of the SOVA decode where n is greater than 1;an nT reliability measurement unit (RMU) circuit coupled to receive the nT clock signal pulses, the RMU circuit adapted to receive 1T input signals from the SOVA decoder, the RMU circuit further adapted to output n log-likelihood ratio (LLR) values in response to each nT clock pulse signal, the LLR values based on the received 1T input signals, the n LLR values used by the SOVA decoder to determine a most likely output for a received symbol. 7. The circuit of claim 6wherein the RMU circuit further comprises:a plurality of slices each adapted to generate n LLR values to advance the LLR value computation to a next depth of a predetermined fixed depth, each slice coupled to receive n state metric difference (SMD) values from the SOVA decoder, each slice coupled to receive path equivalency information values from the SOVA decoder, each slice coupled to receive n LLR values relating to a preceding nT clock signal pulse, each slice adapted to generate n LLR values based on the received SMD values and the received path equivalency information values and the received LLR values. 8. The circuit of claim 7where n is 2,wherein the received SMD values received at nT clock pulse number t are SMDt-1 and SMDt,wherein the path equivalency information values received at nT clock pulse number t are EQXt-1, EQYt, EQYt-1, and EQZt, andwherein each slice is adapted to generate 2 LLR values responsive to nT clock pulse number t as Yt and Zt as: if (EQYt=1) & (EQXt-1=1) then Yt=Wt-2 if (EQYt=1) & (EQXt-1=0) then Yt=min(Wt-2, SMDt-1)if (EQYt=0) & (EQXt-1=1) then Yt=min(Wt-2, SMDt)if (EQYt=0) & (EQXt-1=0) then Yt=min(Wt-2, SMDt-1, SMDt)if (EQZt=1) & (EQYt-1=1) then Zt=Xt-2 if (EQZt=1) & (EQYt-1=0) then Zt=min(Xt-2, SMDt-1)if (EQZt=0) & (EQYt-1=1) then Zt=min(Xt-2, SMDt)if (EQZt=0) & (EQYt-1=0) then Zt=min(Xt-2, SMDt-1, SMDt),where:min is a function that determines the minimum value of listed parameters,Wt-2 is an LLR value relating to a preceding nT clock signal pulse, andXt-2 is an LLR value relating to a preceding nT clock signal pulse. 9. The circuit of claim 8wherein a last slice is further adapted to generate final LLR values including Zt as above and Zt-1 as: if (EQZt-1=1) then Zt-1=min(Yt-2, SMDt-1)if (EQZt-1=0) then Zt-1=Yt-2. 10. The circuit of claim 8wherein the first slice is adapted to receive initial LLR values representing highest confidence as Wt-2 and Xt-2 input values. 11. The circuit of claim 7wherein the RMU processes inputs to a predetermined depth “M”, andwherein the number of slices in the plurality of slices is M/n.