초록 ▼

A system having a graphical compiler connected to a function block engine. The graphical compiler may convert graphical information to non-graphical information. A resources allocation module may be connected to the function block engine and the compiler. Also, a function block execution list may be

A system having a graphical compiler connected to a function block engine. The graphical compiler may convert graphical information to non-graphical information. A resources allocation module may be connected to the function block engine and the compiler. Also, a function block execution list may be connected to the compiler and the function block engine. A user interface may be connected to the compiler.

대표청구항 ▼

1. A control system language compiler method comprising: loading control functions into a memory associated with the control system language compiler;initiating a control loop design structure; andinstantiating the control loop design structure; andconfiguring a circuit or structure designed using t

1. A control system language compiler method comprising: loading control functions into a memory associated with the control system language compiler;initiating a control loop design structure; andinstantiating the control loop design structure; andconfiguring a circuit or structure designed using the control loop design structure to operate using a function block engine to execute a function block execution list as a list of references to functions and/or data, wherein the function block engine operates within a specified amount of memory allocated in the memory of a controller;entering a configuration mode of the control loop design structure for designing a circuit or structure;designing a circuit or structure which includes dragging function and/or non-function blocks onto a display screen; andconnecting the function and/or non-function blocks to effect a design of the circuit or structure. 2. The method of claim 1, further comprising compiling graphical information of the design of the circuit or structure into information in a non-graphical format. 3. The method of claim 2, wherein the non-graphical format is a comma separated value format. 4. The method of claim 2, further comprising allocating memory resources for the information in the non-graphical format. 5. The method of claim 4, further comprising: providing a tool storage file; andstoring the information of the non-graphical format in the tool storage file. 6. The method of claim 5, further comprising: entering a simulation mode for testing the design of the circuit or structure; andmaking configuration, parameter, summary and/or debug files. 7. The method of claim 1, further comprising compiling graphical information of the design into a configuration file. 8. A system comprising: a controller having a fixed amount memory and comprising a function block engine; anda computer comprising a graphical compiler module, the graphical compiler module configured to output a function block execution list used by the function block engine; andwherein:the function block execution list includes a listing of one or more references to function blocks and an order of execution of the function blocks by the function block engine;entering a configuration mode of the control loop design structure is for designing a circuit or structure;designing a circuit or structure includes dragging function and/or non-function blocks onto a display screen; andconnecting the function and/or non-function blocks effects a design of the circuit or structure. 9. The system of claim 8, further comprising a function block allocation resources module connected to the function block engine and the graphical compiler module. 10. The system of claim 8, further comprising a function block execution list module connected to the graphical compiler module. 11. The system of claim 8, further comprising a user interface connected to the graphical compiler module. 12. The system of claim 8, wherein the graphical compiler module comprises converting graphical information into non-graphical information. 13. A method comprising: initiating a graphical compiler module structure;configuring function blocks, parameters, interconnects for the graphical compiler module;activating a memory resource module; andgenerating configuration information for the function blocks;generating a function block execution list from the configured graphical compiler module;executing the function block execution list by a function block engine using the configuration information within a specified amount of memory allocated in random access memory (RAM) of an embedded controller;entering a configuration mode of the control loop design structure for designing a circuit or structure;designing a circuit or structure which includes dragging function and/or non-function blocks onto a display screen; andconnecting the function and/or non-function blocks to effect a design of the circuit or structure. 14. The method of claim 13, further comprising generating configuration information for non-function blocks. 15. The method of claim 14, further comprising translating graphical design information into function blocks configuration information. 16. The method of claim 15, further comprising translating graphical design information into non-function block configuration information. 17. The method of claim 16, further comprising converting the function block and non-function block configuration information into an intermediate format. 18. The method of claim 17, wherein the intermediate format is a comma separated value format. 19. The method of claim 13, wherein a specified amount of random access memory (RAM) is about 1 kilobyte.