초록 ▼

A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit

A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.

대표청구항 ▼

1. A semiconductor chip comprising: a semiconductor substrate;a copper interconnect over said semiconductor substrate;a first metal layer at a bottom of said copper interconnect and at a sidewall of said copper interconnect;an insulating layer over said semiconductor substrate and on a top surface o

1. A semiconductor chip comprising: a semiconductor substrate;a copper interconnect over said semiconductor substrate;a first metal layer at a bottom of said copper interconnect and at a sidewall of said copper interconnect;an insulating layer over said semiconductor substrate and on a top surface of said copper interconnect, wherein a first opening in said insulating layer is over a first contact point of said copper interconnect, wherein said insulating layer comprises a nitride;a second metal layer on said first contact point and on a top surface of said insulating layer;a third metal layer on said second metal layer, wherein said third metal layer is connected to said first contact point through said first opening;a passivation layer on a top surface of said third metal layer and on said insulating layer, wherein a second opening in said passivation layer is over a second contact point of an aluminum-containing layer of said third metal layer, wherein said passivation layer comprises a nitride;a fourth metal layer on said second contact point and on a top surface of said passivation layer;a gold seed layer on said fourth metal layer; andan electroplated gold layer on said gold seed layer, wherein said electroplated gold layer is configured for connecting with an external circuit in a chip-on-film (COF) package, wherein said electroplated gold layer has a thickness between 5 and 25 micrometers. 2. The semiconductor chip of claim 1, wherein said first metal layer comprises a tantalum-containing layer. 3. The semiconductor chip of claim 1, wherein said second metal layer comprises tantalum. 4. The semiconductor chip of claim 1, wherein said second metal layer comprises titanium. 5. The semiconductor chip of claim 1, wherein said fourth metal layer comprises titanium. 6. The semiconductor chip of claim 1, wherein said aluminum-containing layer has a thickness between 0.5 and 5 micrometers. 7. The semiconductor chip of claim 1, wherein said semiconductor substrate comprises a silicon substrate. 8. The semiconductor chip of claim 1, wherein said nitride of said passivation layer has a thickness greater than 0.3 micrometers. 9. The semiconductor chip of claim 1, wherein said nitride of said insulating has a thickness greater than 0.3 micrometers. 10. The semiconductor chip of claim 1, wherein said second opening has a width between 2 and 40 micrometers. 11. A semiconductor chip comprising: a semiconductor substrate;a first dielectric layer over said semiconductor substrate;a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal interconnect and a second metal interconnect over said first metal interconnect, wherein said second metal interconnect comprises electroplated copper and a first metal layer at a bottom and sidewall of said electroplated copper of said second metal interconnect;a second dielectric layer between said first and second metal interconnects;a third dielectric layer over said metallization structure and said first and second dielectric layers, wherein a first opening in said third dielectric layer is over a first contact point of said second metal interconnect, and said first contact point is at a bottom of said first opening;a third metal interconnect on said third dielectric layer and said first contact point, wherein said third metal interconnect comprises a second metal layer and an aluminum-containing layer on said second metal layer;a passivation layer on said third metal interconnect and said third dielectric layer, wherein a second opening in said passivation layer is over a second contact point of said third metal interconnect, and said second contact point is at a bottom of said second opening;a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said second contact point;a fourth metal interconnect on said first polymer layer and said second contact point, wherein said fourth metal interconnect comprises an adhesion metal layer, a copper-containing seed layer on said adhesion metal layer, an electroplated copper layer on said copper-containing seed layer and a nickel-containing layer on said electroplated copper layer of said fourth metal interconnect; anda second polymer layer on said fourth metal interconnect and said first polymer layer, wherein a fourth opening in said second polymer layer is over a third contact point of said fourth metal interconnect, and said third contact point is at a bottom of said fourth opening, wherein said third contact point is not vertically over said second contact point. 12. The semiconductor chip of claim 11, wherein said first metal layer comprises tantalum. 13. The semiconductor chip of claim 11, wherein said second metal layer comprises titanium. 14. The semiconductor chip of claim 11, wherein said second metal layer comprises tantalum. 15. The semiconductor chip of claim 11, wherein said adhesion metal layer comprises titanium.