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Device including a field having function cells and information providing cells controlled by the function cells 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/30
출원번호 US-0490081 (2002-09-19)
등록번호 US-8429385 (2013-04-23)
우선권정보 DE-101 46 132 (2001-09-19); DE-101 54 259 (2001-11-05); EP-01129923 (2001-12-14); EP-02001331 (2002-01-18); DE-102 06 653 (2002-02-15); DE-102 06 856 (2002-02-18); DE-102 06 857 (2002-02-18); DE-102 07 224 (2002-02-21); DE-102 07 226 (2002-02-21); DE-102 08 434 (2002-02-27); DE-102 08 435 (2002-02-27); DE-102 12 621 (2002-03-21); DE-102 12 622 (2002-03-21); DE-102 19 681 (2002-05-02); EP-02009868 (2002-05-02); DE-102 26 186 (2002-06-12); DE-102 27 650 (2002-06-20); DE-102 36 269 (2002-08-07); DE-102 36 271 (2002-08-07); DE-102 36 272 (2002-08-07); DE-102 38 174 (2002-08-21); DE-102 385 172 (2002-08-21); DE-102 385 173 (2002-08-21); DE-102 40 000 (2002-08-27); DE-102 40 022 (2002-08-27); DE-102 41 812 (2002-09-06)
국제출원번호 PCT/EP02/10572 (2002-09-19)
§371/§102 date 20041129 (20041129)
국제공개번호 WO03/036507 (2003-05-01)
발명자 / 주소
  • Vorbach, Martin
출원인 / 주소
  • Vorbach, Martin
대리인 / 주소
    Kenyon and Kenyon LLP
인용정보 피인용 횟수 : 1  인용 특허 : 558

초록

A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

대표청구항

1. A method for operating a multidimensional cell element field having function cells for the execution of at least one of algebraic and logic functions and information-providing cells that include at least one of memory cells and input-output cells for at least one of receiving, storing, and output

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  188. Chen Duan-Ping, High speed logic circuit simulator.
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  220. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.
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  229. Mirsky, Ethan; French, Robert; Eslick, Ian, Local control of multiple context processing elements with major contexts and minor contexts.
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  243. Matsushima Koh,JPX ; Wakasu Yutaka,JPX, Memory access controller.
  244. Olgiati, Andrea; McCarthy, Dominic Paul, Memory and instructions in computer architecture containing processor and coprocessor.
  245. Higginbottom Raymond Paul,AUX, Memory controller architecture.
  246. Manning, Troy A., Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times.
  247. Williams Brett ; Schaefer Scott, Memory device having circuitry for initializing and reprogramming a control operation feature.
  248. Jones Christopher W., Memory in a programmable logic device.
  249. Hyatt Gilbert P. (7841 Jennifer Cir. La Palma CA 90623), Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit.
  250. Horst Robert W. (Champaign IL), Memory system using linear array wafer scale integration architecture.
  251. Dolecek Quentin E. (Silver Spring MD), Memory-linked wavefront array processor.
  252. Lefebvre Martin C. (Ottawa CAX) Ciancibello Carmine A. (Nepean CAX) Geadah Youssef A. (Nepean CAX), Message FIFO buffer controller.
  253. Kessler Richard E. ; Oberlin Steven M. ; Scott Steven L., Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queu.
  254. Kuijsten Han (Oakland CA), Method and apparatus for a trace buffer in an emulation system.
  255. Magloire Alexander B., Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device.
  256. Juan, Yujen, Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration.
  257. Wu Frank Y., Method and apparatus for contiguously addressing a memory system having vertically expanded multiple memory arrays.
  258. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont.
  259. Ethan Mirsky ; Robert French ; Ian Eslick, Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements.
  260. McWilliams,Thomas M.; Rubin,Jeffrey B.; Pappas,Derek E.; Olukotun,Oyekunle A.; Broughton,Jeffrey M.; Emberson,David R.; Lam,William kwei cheung; Chen,Liang T.; Chen,Ihao; Cohen,Earl T.; Parkin,Michae, Method and apparatus for cycle-based computation.
  261. Liu Dick L. (Saratoga CA) Li Jeong-Tyng (Cupertino CA) Huang Thomas B. (San Jose CA) Choi Kenneth S. K. (San Jose CA), Method and apparatus for debugging reconfigurable emulation systems.
  262. Burke, David, Method and apparatus for executing standard functions in a computer system using a field programmable gate array.
  263. Rodgers Scott Dion ; Vidwans Rohit ; Huang Joel ; Fetterman Michael A. ; Huck Kamla, Method and apparatus for generating event handler vectors based on both operating mode and event type.
  264. Jones Christopher W., Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit.
  265. Bernard J. New ; Steven P. Young, Method and apparatus for incorporating a multiplier into an FPGA.
  266. Matter Eugene P. (Folsom CA) Sotoudeh Yahya S. (Santa Clara CA) Mathews Gregory S. (Boca Raton FL), Method and apparatus for independently stopping and restarting functional units.
  267. Matter Eugene P. (Folsom CA) Sotoudeh Yahya S. (Santa Clara CA) Mathews Gregory S. (Boca Raton FL), Method and apparatus for independently stopping and restarting functional units.
  268. King Edward C. (4945 Norris Rd. Fremont CA 94536) Adams John M. (6313 Vail Cir. Colorado Springs CO 80919), Method and apparatus for managing video data for faster access by selectively caching video data.
  269. Kan Larry Yiucham ; Anderson William C. ; Hung Chuan-Chang ; Bell Meltin, Method and apparatus for moving data in a parallel processor.
  270. Moore, Michael T., Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD).
  271. Barbier Jean,FRX ; LePape Olivier,FRX ; Reblewski Frederic,FRX, Method and apparatus for performing fully visible tracing of an emulation.
  272. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for position independent reconfiguration in a network of multiple context processing elements.
  273. Parikh Shrikant N. (Mesquite TX), Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesse.
  274. Saito Masahiko,JPX ; Kurosawa Kenichi,JPX ; Kobayashi Yoshiki,JPX ; Bandoh Tadaaki,JPX ; Iwamura Masahiro,JPX ; Hotta Takashi,JPX ; Nakatsuka Yasuhiro,JPX ; Tanaka Shigeya,JPX ; Takemoto Takeshi,JPX, Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memo.
  275. Takano Toshiya (Hokkaido JPX), Method and apparatus for processing interruption.
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  277. Hu King Seng (Penang MYX) Liew Vui Yong (Penang MYX), Method and apparatus for providing power saving modes to a pipelined processor.
  278. Simmons Laura E. ; Jayavant Rajeev, Method and apparatus for reducing power consumption in digital electronic circuits.
  279. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for retiming in a network of multiple context processing elements.
  280. Abramovici Miron ; Stroud Charles Eugene ; Wijesuriya Sajitha S., Method and apparatus for testing field programmable gate arrays.
  281. Matsumoto Takashi (Hadano JPX), Method and apparatus for testing logic circuitry by applying a logical test pattern.
  282. Mercs, James, Method and apparatus for the allocation of audio/video tasks in a network system.
  283. Hanna, Stephen Dale, Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits.
  284. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.
  285. Pani,Peter M.; Ting,Benjamin S., Method and apparatus for universal program controlled bus architecture.
  286. Stansfield, Anthony; Marshall, Alan David; Vuillemin, Jean, Method and apparatus for varying instruction streams provided to a processing device using masks.
  287. Borkenhagen John Michael ; Eickemeyer Richard James ; Flynn William Thomas ; Wottreng Andrew Henry, Method and apparatus to force a thread switch in a multithreaded processor.
  288. Sato, Makoto; Hirooka, Takashi, Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing.
  289. Wulf William A. ; McKee Sally A. ; Klenke Robert ; Schwab Andrew J. ; Moyer Stephen A. ; Aylor James ; Hitchcock Charles Young, Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order.
  290. Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, Method and structure for configuring FPGAS.
  291. Earl William J., Method and system for an efficient user mode cache manipulation using a simulated instruction.
  292. Dangelo Carlos ; Watkins Daniel ; Mintz Doron, Method and system for creating and validating low level description of electronic design from higher level, behavior-or.
  293. Blainey Robert James,CAX, Method and system for determining inter-compilation unit alias information.
  294. Agarwal Ramesh C. (Yorktown Heights NY) Groves Randall D. (Austin TX) Gustavson Fred G. (Briarcliff Manor NY) Johnson Mark A. (Austin TX) Olsson Brett (Round Rock TX), Method and system for dynamically reconfiguring a register file in a vector processor.
  295. Barroso, Luiz Andre; Gharachorloo, Kourosh; Nowatzyk, Andreas, Method and system for exclusive two-level caching in a chip-multiprocessor.
  296. Craft David John ; Gould Scott Whitney ; Keyser ; III Frank Ray ; Worth Brian, Method and system for programming a gate array using a compressed configuration bit stream.
  297. Lewis, Michael C., Method and system for providing a flexible and efficient processor for use in a graphics processing system.
  298. Stearns Charles C. (San Jose CA) Kannappan Karthikeyan (San Jose CA), Method for 2-D affine transformation of images.
  299. Hunt Peter D. (Pleasanton CA) Elliott Jon K. (Pleasanton CA) Tobias Richard J. (San Jose CA) Herring Alan J. (San Jose CA) Morgan Craig R. (San Jose CA) Hiller John A. (Palo Alto CA), Method for automated deployment of a software program onto a multi-processor architecture.
  300. Trimberger Stephen M., Method for compiling and executing programs for reprogrammable instruction set accelerator.
  301. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
  302. Cooke, Laurence H.; Phillips, Christopher E.; Wong, Dale, Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic.
  303. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
  304. Weisenborn Gerald M. (Ruckersville VA), Method for converting a programmable logic controller hardware configuration and corresponding control program for use o.
  305. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
  306. Powell Douglas B. (San Francisco CA), Method for deriving optimal code schedule sequences from synchronous dataflow graphs.
  307. Ku.cedilla.uk.cedilla.akar Kayhan, Method for designing a product having hardware and software components and product therefor.
  308. Sven Wuytack BE; Francky Catthoor BE; Hugo De Man BE, Method for determining a storage bandwidth optimized memory organization of an essentially digital device.
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  311. Henzinger Monika Hildegard ; Leung Shun-Tak Albert ; Sites Richard L. ; Vandevoorde Mark T. ; Weihl William Edward, Method for identifying reasons for dynamic stall cycles during the execution of a program.
  312. Carr Charles F., Method for making herringbone gears.
  313. Pickett Scott K. (San Jose CA) Luich Thomas M. (Campbell CA) Swift ; IV Arthur L. (Welches OR), Method for operating a multiple page programmable logic device.
  314. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  318. May,Frank; N?ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
  319. Hussein, Jameel; Moss, Dean C.; Walstrum, Jr., James A., Method of and system for verifying configuration data.
  320. Guccione Steven A., Method of designing FPGAs for dynamically reconfigurable computing.
  321. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
  322. Guccione, Steven A.; McMillan, Scott P., Method of partial reconfiguration of a PLD in which only updated portions of configuration data are selected for reconfiguring the PLD.
  323. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
  324. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
  325. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
  326. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
  327. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
  328. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  329. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  330. Butts, Michael R.; Batcheller, Jon A., Method of using electronically reconfigurable logic circuits.
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  332. Megiddo Nimrod ; Sarkar Vivek, Method of, system for, and computer program product for performing weighted loop fusion by an optimizing compiler.
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  344. Casselman Steve M., Modular, hybrid processor and method for producing a modular, hybrid processor.
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  346. Mavity John C. (Kinburn CAX), Multi-media server.
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이 특허를 인용한 특허 (1)

  1. Tatsumura, Kosuke; Zaitsu, Koichiro, Reconfigurable circuit including row address replacement circuit for replacing defective address.
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