최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0354702 (2012-01-20) |
등록번호 | US-8433023 (2013-04-30) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 297 |
A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select
A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The delay value of a voltage-controlled delay circuit and the phase relationship between the first and second clock signals to a predetermined phase relationship are thereby adjusted.
1. A computer system, comprising: a processor having a processor bus;an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;an output device coupled to the processor through the processor bus adapted to allow data to be output
1. A computer system, comprising: a processor having a processor bus;an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; anda memory coupled to the processor bus adapted to allow data to be stored, the memory comprising:a command data latch circuit for storing a command data packet at a time determined from a command clock signal, the command data latch comprising:a latch circuit having a data input and a clock input, the data input being adapted to receive the command data packet and store the command data packet responsive to a clock signal applied to the clock input; anda clock generator circuit for generating a latch signal from a master clock signal, the clock generator circuit comprising:a first delay-lock loop having a first voltage controlled delay circuit receiving a reference clock signal and generating a sequence of clock signals which are increasingly delayed from the reference clock signal to a last clock signal by delaying the reference clock signal by respective delays that are a function of a first control signal, anda phase detector comparing the phase of first and second clock signals in the sequence and generating the first control signal as a function of the phase difference therebetween, the phase detector comprising:a first input configured to receive the first clock signal;a second input configured to receive the second clock signal; anda charge pump comprising an output terminal, a first current source, and a second current source, and wherein the charge pump is configured to cause the first and second current sources to bypass the output terminal responsive to the first and second clock signals being substantially in phase,wherein the charge pump comprises a first switching device and a second switching device coupled in series between the first current source and the output terminal, and wherein one of the first and second switching devices is configured to substantially prevent current flow between the first current source and the output terminal responsive to the first and second clock signals being in phase, and;wherein the charge pump comprises a third switching device and a fourth switching device coupled in series between the second current source and the output terminal, and wherein one of the third and fourth switching devices is configured to substantially prevent current flow between the second current source and the output terminal responsive to the first and second clock signals being in phase. 2. The computer system of claim 1, wherein the charge pump is further configured to couple the first current source to the output terminal responsive to the first clock signal leading the second clock signal. 3. The computer system of claim 2, wherein the charge pump is further configured to couple the second current source to the output terminal responsive to the first clock signal lagging the second clock signal. 4. The computer system of claim 1, wherein the first and second switching devices are configured to substantially allow current flow between the first current source and the output terminal responsive to the first clock signal leading the second clock signal. 5. The computer system of claim 1, wherein the third and fourth switching devices are configured to substantially allow current flow between the second current source and the output terminal responsive to the first clock signal lagging the second clock signal. 6. The computer system of claim 1, further comprising: a first phase detector circuit configured to receive the first and second clock signals and generate a first control signal indicative of a time between a rising edge of the second clock signal and a falling edge of the first clock signal;a second phase detector circuit configured to receive the first and second clock signals and generate a second control signal indicative of a time between a rising edge of the first clock signal and a falling edge of the second clock signal; andwherein the first and third switching devices are configured to receive the first control signal and wherein the second and fourth switching devices are configured to receive the second control signal. 7. The phase detector of claim 1, further comprising a compensation circuit coupled between the first and second current sources and configured to maintain a substantially constant voltage between the first and second current sources. 8. A computer system, comprising: a processor having a processor bus;an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; anda memory coupled to the processor bus adapted to allow data to be stored, the memory comprising:a command data latch circuit for storing a command data packet at a time determined from a command clock signal, the command data latch comprising: a latch circuit having a data input and a clock input, the data input being adapted to receive the command data packet and store the command data packet responsive to a clock signal applied to the clock input; anda clock generator circuit for generating a latch signal from a master clock signal, the clock generator circuit having a phase detector, for providing a control signal according to the phase relationship between first and second clock signals, the phase detector comprising:a first input configured to receive the first clock signal;a second input configured to receive the second clock signal; anda charge pump comprising an output terminal, a first current source, and a second current source, and wherein the charge pump is configured to cause the first and second current sources to bypass the output terminal responsive to the first and second clock signals being substantially in phase,wherein the charge pump comprises a first switching device and a second switching device coupled in series between the first current source and the output terminal, and wherein one of the first and second switching devices is configured to substantially prevent current flow between the first current source and the output terminal responsive to the first and second clock signals being in phase, and;wherein the charge pump comprises a third switching device and a fourth switching device coupled in series between the second current source and the output terminal, and wherein one of the third and fourth switching devices is configured to substantially prevent current flow between the second current source and the output terminal responsive to the first and second clock signals being in phase. 9. The computer system of claim 8, wherein the charge pump is further configured to couple the first current source to the output terminal responsive to the first clock signal leading the second clock signal. 10. The computer system of claim 9, wherein the charge pump is further configured to couple the second current source to the output terminal responsive to the first clock signal lagging the second clock signal. 11. The computer system of claim 8, wherein the first and second switching devices are configured to substantially allow current flow between the first current source and the output terminal responsive to the first clock signal leading the second clock signal. 12. The computer system of claim 8, wherein the third and fourth switching devices are configured to substantially allow current flow between the second current source and the output terminal responsive to the first clock signal lagging the second clock signal. 13. The computer system of claim 8, further comprising: a first phase detector circuit configured to receive the first and second clock signals and generate a first control signal indicative of a time between a rising edge of the second clock signal and a falling edge of the first clock signal;a second phase detector circuit configured to receive the first and second clock signals and generate a second control signal indicative of a time between a rising edge of the first clock signal and a falling edge of the second clock signal; andwherein the first and third switching devices are configured to receive the first control signal and wherein the second and fourth switching devices are configured to receive the second control signal. 14. The computer system of claim 8, further comprising a compensation circuit coupled between the first and second current sources and configured to maintain a substantially constant voltage between the first and second current sources. 15. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; anda memory coupled to the processor bus adapted to allow data to be stored, the memory comprising:a command data latch circuit for storing a command data packet at a time determined from a command clock signal, the command data latch comprising:a latch circuit having a data input and a clock input, the data input being adapted to receive the command data packet and store the command data packet responsive to a clock signal applied to the clock input; anda clock generator circuit for generating a latch signal from a master clock signal, the clock generator circuit comprising:a variable delay unit configured to receive the clock signal and generate a delayed clock signal by an amount based in part on a first control signal, wherein the variable delay unit includes a multi-tap variable delay unit having a plurality of taps, each tap configured to output an intermediate clock signal having a respective delay relative to the clock signal, a delay between at least two of the intermediate clock signals being based in part on a second control signal received by the multi-tap variable delay unit;a first phase detector configured to receive the clock signal and the delayed clock signal and configured to generate the first control signal based on a phase relationship between the clock signal and the delayed clock signal, wherein the first phase detector is further configured to maintain a substantially constant first control signal responsive to the clock signal and the delayed clock signal having a selected phase relationship; anda second phase detector configured to receive the at least two intermediate clock signals and generate the second control signal based on a phase relationship between the two intermediate clock signals, wherein the second phase detector is further configured to maintain a substantially constant second control signal responsive to the at least two intermediate clock signals having another selected phase relationship. 16. The computer system of claim 15, wherein the first phase detector is further configured to adjust the control signal in a first direction responsive to an indication the clock signal leads the delayed clock signal by an amount greater than that of the selected phase relationship, and wherein the first phase detector is further configured to adjust the control signal in a second direction responsive to an indication the clock signal lags the delayed clock signal by an amount greater than that of the selected phase relationship. 17. The computer system of claim 15, further comprising: a multiplexer configured to receive the intermediate clock signals generated by the multi-tap variable delay unit and select at least one of the intermediate clock signals to couple to another circuit element; anda simulated multiplexer coupled between one of the taps of the multi-tap variable delay unit and the first phase detector, the simulated multiplexer configured to simulate a delay generated by the multiplexer. 18. The computer system of claim 15, wherein the phase detector comprises: a charge pump comprising an output terminal, a first current source, and a second current source, and wherein the charge pump is configured to cause the first and second current sources to bypass the output terminal responsive to the clock signal and the delayed clock signal having the selected phase relationship. 19. The computer system of claim 18, wherein the charge pump further comprises a first and a second switching device coupled in series between the first current source and the output terminal, and wherein one of the first and second switching devices are configured to substantially prevent current flow between the first current source and the output terminal responsive to the clock signal and the delayed clock signals having the selected phase relationship.
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