$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Analog bus sharing using transmission gates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03L-005/00
  • H01L-025/00
출원번호 US-0496579 (2009-07-01)
등록번호 US-8441298 (2013-05-14)
발명자 / 주소
  • Williams, Timothy
  • Wright, David G.
  • Kutz, Harold
  • Thiagarajan, Eashwar
  • Snyder, Warren
  • Hastings, Mark E.
출원인 / 주소
  • Cypress Semiconductor Corporation
인용정보 피인용 횟수 : 8  인용 특허 : 44

초록

In one example, a chip includes an integrated analog component configured to communicate over an internal analog bus of the chip. A plurality of I/O pads located on the chip is configured to provide a connected device access to the integrated analog component. A plurality of transmission gates confi

대표청구항

1. An apparatus, comprising: a chip having an integrated analog component configured to communicate over an internal analog bus of the chip;a plurality of I/O pads located on the chip and configured to provide a connected device access to the integrated analog component, wherein each I/O pad is coup

이 특허에 인용된 특허 (44)

  1. Early,Adrian; Kutz,Harold, Analog I/O with digital signal processor array.
  2. Hoeld Wolfgang K. (Moorenweis DEX), Analog multiplexer cell for mixed digital and analog signal inputs.
  3. Sriram R. Vangal ; Matthew B. Haycock ; Stephen R. Mooney, Biased control loop circuit for setting impedance of output driver.
  4. Haycock, Matthew B.; Mooney, Stephen R.; Martin, Aaron K., Bidirectional port with clock channel used for synchronization.
  5. Ng Richard ; Mottier Matthew Duane ; Janssen John Jerome, Bidirectional voltage translator.
  6. Gorecki, James L.; Gazeley, Bill G.; Yang, Yaohua, Double differential comparator and programmable analog block architecture using same.
  7. Pleis,Matthew A.; Ogami,Kenneth Y., Dynamic reconfiguration interrupt system and method.
  8. Dobbelaere Ivo J. (Palo Alto CA) El Gamal Abbas (Palo Alto CA), Electrically programmable inter-chip interconnect architecture.
  9. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array with distributed RAM and increased cell utilization.
  10. Plants William C. (Santa Clara CA) Kaptanoglu Sinan (San Carlos CA) Lien Jung-Cheun (San Jose CA) Chan King W. (Los Altos CA) El-Ayat Khaled A. (Cupertino CA), Flexible FPGA input/output architecture.
  11. Borkar Shekhar (Portland OR) Mooney Stephen R. (Beaverton OR) Dike Charles E. (Hillsboro OR), High speed bidirectional signaling scheme.
  12. Zaliznyak Arch ; Bobra Yogendra K. ; Kola Madhavi, High-speed programmable logic architecture having active CMOS device drivers.
  13. Klein, Hans W.; Li, Jian; Hildebrant, Paul, Highly linear programmable transconductor with large input-signal range.
  14. Rogers,J. Clark; Kris,Bryan, Integrated circuit device having at least one of a plurality of bond pads with a selectable plurality of input-output functionalities.
  15. Moyer, William C.; Kelley, John, Method and apparatus for controlling a data processing system during debug.
  16. Tani,Keisuke; Obayashi,Kazuyoshi, Method and apparatus for driving and controlling on-vehicle loads.
  17. Sanchez, Reno L.; Linn, John H., Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC).
  18. Sanchez,Reno L.; Linn,John H., Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC).
  19. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  20. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
  21. Vorbach, Martin, Methods and devices for treating and/or processing data.
  22. Jose Maria Insenser Farre ES; Julio Faura Enriquez ES, Microprocessor based mixed signal field programmable integrated device and prototyping methodology.
  23. Kutz, Harold; Mar, Monte; Snyder, Warren, Multiple use of microcontroller pad.
  24. Anderson David J. ; Bersch Danny A., Programmable analog array and method.
  25. Bertolet Allan Robert (Williston VT) Ferguson Kenneth (Edinburgh GB6) Gould Scott Whitney (South Burlington VT) Millham Eric Ernest (St. George VT) Palmer Ronald Raymond (Westford VT) Worth Brian (Mi, Programmable array I/O-routing resource.
  26. Piasecki,Douglas S.; Storvik, II,Alvin C., Programmable driver for an I/O pin of an integrated circuit.
  27. Dao,Khang Kim; Baxter,Glenn A., Programmable logic device including programmable interface core and central processing unit.
  28. Gudger Keith H. (Sunnyvale CA) Gongwer Geoffrey S. (San Jose CA), Programmable logic device with global and local product terms.
  29. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device with hierarchical confiquration and state storage.
  30. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture (mixed analog/digital).
  31. Hastings Roy A. (Allen TX) Neale Todd M. (Carrollton TX) Whitney Brad (Anaheim CA), Programmable mixed-mode integrated circuit architecture.
  32. Bakker, Greg; El Ayat, Khaled; Speers, Theodore; Zhu, Limin; Schubert, Brian; Balasubramanian, Rabindranath; Kolkind, Kurt; Barraza, Thomas; Narayanan, Venkatesh; McCollum, John; Plants, William C., Programmable system on a chip.
  33. Son, Jae S.; Ables, David; Dobie, Gordon, Reconfigurable tactile sensor input device.
  34. Pleis,Matthew A.; Sullam,Bert; Lesher,Todd, Reconfigurable testing system and method.
  35. Lau,Benedict C., Scalable I/O signaling topology using source-calibrated reference voltages.
  36. Nickolls John R. (Los Altos CA) Zapisek John (Cupertino CA) Kim Won S. (Fremont CA) Kalb Jeffrey C. (Saratoga CA) Blank W. Thomas (Palo Alto CA) Wegbreit Eliot (Palo Alto CA) Van Horn Kevin (Mountain, Scalable processor to processor and processor to I/O interconnection network and method for parallel processing arrays.
  37. Chang Nai-Shung,TWX, Signal converter with a dynamically adjustable reference voltage and chipset including the same.
  38. Kim, Woo-Seop, Simultaneous bidirectional input/output circuit and method.
  39. Lin,Mou Shiung, Software programmable multiple function integrated circuit module.
  40. Pleis, Matthew A.; Ogami, Kenneth Y.; Snyder, Warren, System and method of dynamically reconfiguring a programmable integrated circuit.
  41. Martin,Nick; Stankovic,Dejan; Wells,Ben; Crasta,Denzil; Russell,Johnny F.; Rodway,Michael, System for designing re-programmable digital hardware platforms.
  42. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
  43. Baker Robert K. ; Kayser Frank ; Bao Jianming ; Kotliar Andrew ; Parsons William H. ; Rupprecht Kathleen M., Triterpene derivatives with immunosuppressant activity.
  44. Whitten Ralph G. (San Jose CA), Two-stage programmable interconnect architecture.

이 특허를 인용한 특허 (8)

  1. Williams, Timothy J.; Kutz, Harold; Wright, David G.; Thiagarajan, Eashwar; Snyder, Warren S.; Hastings, Mark E., Bus sharing scheme.
  2. Williams, Timothy J.; Wright, David G.; Kutz, Harold; Thiagarajan, Eashwar; Snyder, Warren S.; Hastings, Mark E, Bus sharing scheme.
  3. Hsieh, Cheng-Che, Bypass circuits and network security devices using the same.
  4. Kutz, Harold M.; Williams, Timothy John; Sullam, Bert S.; Snyder, Warren S.; Shutt, James H.; Byrkett, Bruce E.; Mar, Monte; Thiagarajan, Eashwar; Kohagen, Nathan Wayne; Wright, David G.; Hastings, Mark E; Seguine, Dennis R., Combined analog architecture and functionality in a mixed-signal array.
  5. Kowkutla, Venkateswar Reddy; Bilhan, Erkan; Pothireddy, Venkateswara Reddy, Dual function analog or digital input/output buffer.
  6. Sullam, Bert; Kutz, Harold; Williams, Timothy; Shutt, James; Byrkett, Bruce E.; Richmond, Melany Ann; Kohagen, Nathan; Hastings, Mark; Thiagarajan, Eashwar; Snyder, Warren, Dynamically reconfigurable analog routing circuits and methods for system on a chip.
  7. Williams, Timothy John; Wright, David G.; Verge, Gregory John; Byrkett, Bruce E., Programmable input/output circuit.
  8. Williams, Timothy John; Wright, David G.; Verge, Gregory John; Byrkett, Bruce E., Programmable input/output circuit.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로