IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0814410
(2010-06-11)
|
등록번호 |
US-8441835
(2013-05-14)
|
발명자
/ 주소 |
- Jo, Sung Hyun
- Nazarian, Hagop
- Lu, Wei
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
44 인용 특허 :
87 |
초록
▼
A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersecti
A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.
대표청구항
▼
1. A memory device having a crossbar array, the memory device comprising: a first array of first electrodes extending along a first direction;a second array of second electrodes extending along a second direction;a non-crystalline silicon structure provided between the first electrode and the second
1. A memory device having a crossbar array, the memory device comprising: a first array of first electrodes extending along a first direction;a second array of second electrodes extending along a second direction;a non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array, the non-crystalline silicon structure having a first layer having a first defect density and a second layer having a second defect density different from the first defect density, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell. 2. The memory device of claim 1, wherein the non-crystalline silicon structure includes amorphous silicon. 3. The memory device of claim 1, wherein the first array of the first electrodes are provided over the non-crystalline silicon structure, and the second array of the second electrodes are provided below the non-crystalline silicon structure, and wherein the first array of the first electrodes include silver, the non-crystalline silicon structure includes amorphous silicon, and the second array of the second electrodes include p-type polysilicon. 4. The memory device of claim 3, wherein each of the first and second layers of the non-crystalline structure includes amorphous silicon, the second layer proximate to the second electrode having a greater defect density than the first layer distal from the second electrode to facilitate formation of a filament therein. 5. The memory device of claim 4, wherein the first and second layers comprise substantially the same material. 6. The memory device of claim 4, wherein the first layer has a thickness of no more than 80 nm and the second layer has a thickness of no more than 15 nm. 7. The memory device of claim 4, wherein metal particles are provided at an interface between the second layer and the second electrode. 8. The memory device of claim 1, wherein the second electrodes include a p-type polysilicon contacting the non-crystalline silicon structure and a bottom metal layer provided below the p-type polysilicon. 9. The memory device of claim 1, wherein the two-terminal resistive memory cell is configured to turn ON when a program voltage is applied to the first electrode and turn OFF when an erase voltage is applied to the first electrode, and wherein the two-terminal resistive memory cell is a memory cell that uses a switching medium whose resistance can be controlled by applying electrical signal without ferroelectricity, magnetization and phase change of the switching medium. 10. The memory device of claim 9, wherein the program voltage is 2 to 4 volts and the erase voltage is −2 to −4 volts. 11. The memory device of claim 9, wherein the two-terminal resistive memory cell has a resistance of at least 10E7 Ohm when in an OFF state. 12. The memory device of claim 9, wherein the two-terminal resistive memory cell behaves like a resistor when turned ON and a capacitor when turned OFF. 13. A resistive memory device, comprising: a first electrode;a second electrode;a non-crystalline silicon structure provided between the first electrode and the second electrode, the non-crystalline silicon structure having a first layer having a first defect density and a second layer having a second defect density different from the first defect density, wherein the first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell. 14. The resistive memory device of claim 13, wherein the non-crystalline silicon structure includes amorphous silicon. 15. The resistive memory device of claim 13, wherein the first electrode includes silver, the non-crystalline silicon structure includes amorphous silicon, and the second electrode includes p-type polysilicon. 16. The memory device of claim 15, wherein each of the first and second layers of the non-crystalline structure includes amorphous silicon, the second layer proximate to the second electrode having a greater defect density than the first layer distal from the second electrode to facilitate formation of a filament therein. 17. The memory device of claim 15, wherein the first and second layers comprise substantially the same material, and wherein the first layer has a thickness of no more than 80 nm and the second layer has a thickness of no more than 15 nm. 18. The memory device of claim 15, wherein metal particles are provided at an interface between the second layer and the second electrode. 19. The memory device of claim 13, wherein the two-terminal resistive memory cell is configured to turn ON when a program voltage is applied to the first electrode and turn OFF when an erase voltage is applied to the first electrode, and wherein the two-terminal resistive memory cell behaves like a resistor when turned ON and a capacitor when turned OFF, and wherein the two-terminal resistive memory cell is a memory cell that uses a switching medium whose resistance is changed without ferroelectricity, magnetization and phase change of the switching medium, the non-crystalline silicon structure being the switching medium.
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