Binary conversion circuit and method, AD converter, solid-state imaging device, and camera system
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04N-005/235
H04N-003/14
H03M-001/12
출원번호
US-0659877
(2010-03-24)
등록번호
US-8446483
(2013-05-21)
우선권정보
JP-2009-106961 (2009-04-24)
발명자
/ 주소
Ui, Hiroki
Takahashi, Tomohiro
출원인 / 주소
Sony Corporation
대리인 / 주소
Rader, Fishman & Grauer PLLC
인용정보
피인용 횟수 :
1인용 특허 :
4
초록▼
A binary conversion circuit includes: a latch circuit that latches phase information of at least one clock signal when the level of a signal is inverted, the level of the signal being inverted based on its state; at least one conversion circuit that converts the latched phase information of the latc
A binary conversion circuit includes: a latch circuit that latches phase information of at least one clock signal when the level of a signal is inverted, the level of the signal being inverted based on its state; at least one conversion circuit that converts the latched phase information of the latch circuit to a pulse train in response to a pulse signal; and a ripple counter section that converts phase information of a clock to a binary code by using the pulse obtained by the conversion of the conversion circuit as a count clock.
대표청구항▼
1. A binary conversion circuit comprising: a latch circuit that latches phase information of at least one clock signal when the level of a signal is inverted, the level of the signal being inverted based on its state;at least one conversion circuit that converts the latched phase information of the
1. A binary conversion circuit comprising: a latch circuit that latches phase information of at least one clock signal when the level of a signal is inverted, the level of the signal being inverted based on its state;at least one conversion circuit that converts the latched phase information of the latch circuit to a pulse train in response to a pulse signal; anda ripple counter section that converts phase information of a clock to a binary code by using the pulse obtained by the conversion of the conversion circuit as a count clock,wherein the conversion circuit includes a first conversion circuit and a second conversion circuit,wherein the ripple counter section includes a first ripple counter section and a second ripple counter section,wherein the latch circuit includes four T-type flip-flops that latch different four clock signals, respectively, in which three consecutive T-type flip-flops form a first latch, and a remaining one of the four T-type flip-flops forms a second latch,wherein the binary conversion circuit further includes a selector that selects latched phase information of the three T-type flip-flops serving as the first latch of the latch circuit in response to a select signal, anda mask circuit that performs mask processing for determining whether or not latched phase information of the T-type flip-flop serving as the second latch of the latch circuit will be input to the second conversion circuit in response to a mask signal,wherein the first conversion circuit converts the four pieces of latched phase information of the latch circuit to a pulse train in response to a first pulse signal and outputs the converted signal as a count clock of the first ripple counter section; andwherein the second conversion circuit converts an output signal of the first ripple counter section or the latched phase information of the T-type flip-flop serving as the second latch, supplied via the mask circuit, to a count clock in response to a second pulse signal and outputs the count clock to the second ripple counter section that counts an upper bit. 2. The binary conversion circuit according to claim 1, wherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “0” and “4,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 0 to 7, the decimal numbers being used as the number of pulses. 3. A binary conversion circuit comprising: a latch circuit that latches phase information of at least one clock signal when the level of a signal is inverted, the level of the signal being inverted based on its state;at least one conversion circuit that converts the latched phase information of the latch circuit to a pulse train in response to a pulse signal; anda ripple counter section that converts phase information of a clock to a binary code by using the pulse obtained by the conversion of the conversion circuit as a count clock, wherein the latch circuit includes four T-type flip-flops that latch different four clock signals, respectively, in which three consecutive T-type flip-flops form a first latch, and a remaining one of the four T-type flip-flops forms a second latch,wherein the binary conversion circuit further includes a selector that selects latched phase information of the three T-type flip-flops serving as the first latch of the latch circuit in response to a select signal, andwherein the first conversion circuit converts the four pieces of latched phase information of the latch circuit to a pulse train in response to first and second pulse signals and outputs the converted signal as a count clock of the ripple counter section. 4. The binary conversion circuit according to claim 3, wherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “1” and “2,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 1 to 8, the decimal numbers being used as the number of pulses. 5. A binary conversion method comprising the steps of: latching phase information of at least one clock signal when the level of a signal is inverted, the level of the signal being inverted based on its state;converting the latched phase information to a pulse train in response to a pulse signal; andconverting the phase information to a binary value by using the pulse obtained by the conversion as a count clock of the ripple counter section, wherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “0” and “4,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 0 to 7, the decimal numbers being used as the number of pulses, orwherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “1” and “2,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 1 to 8, the decimal numbers being used as the number of pulses. 6. A binary conversion circuit comprising: a latch circuit configured to receive a clock signal and an output signal, and latch phase information of the clock signal when a level of the output signal is inverted;a conversion circuit configured to receive the latched phase information from the latch circuit and a pulse signal, and convert the latched phase information to a pulse train in response to the pulse signal; anda ripple counter section configured to receive the pulse train as a count clock and convert the phase information of the clock signal to a binary code by using the pulse train as a count clock,wherein the ripple counter section includes an upper-bit ripple counter section and a lower-bit ripple counter section,wherein the upper-bit ripple counter section performs a count operation in response to the clock signal, andwherein the lower-bit ripple counter section performs a count operation based on the phase information of the clock. 7. The binary conversion circuit according to claim 6, wherein the conversion circuit converts the latched phase information to a plurality of pulse trains corresponding to a corresponding binary code. 8. The binary conversion circuit according to claim 6, wherein the latch circuit latches phase information of one clock at a plurality of timings, andwherein the conversion circuit converts the latched phase information of each of the timings to a pulse train. 9. The binary conversion circuit according to claim 8, wherein the conversion circuit converts the phase information to a plurality of pulse trains corresponding to a corresponding binary code. 10. The binary conversion circuit according to claim 6, wherein the upper-bit ripple counter section performs the count operation in response to the count clock or a carry signal from the lower-bit ripple counter section. 11. The binary conversion circuit according to claim 10, further comprising a selection section that selects either the count clock or the carry signal from the lower-bit ripple counter section to be supplied to the upper-bit ripple counter section. 12. An analog-to-digital (AD) converter comprising: a comparator configured to compare an input voltage with a reference voltage having a ramp waveform whose voltage value varies linearly with time; andthe binary conversion circuit according to claim 6;wherein the output signal is output by the comparator, the output signal having a level corresponding to a comparison result. 13. A solid-state imaging device comprising: a pixel section including a plurality of pixels arranged in a matrix form, each of the pixels being configured to perform a photoelectric conversion; anda pixel signal readout section that reads out a pixel signal from the pixel section in units of a plurality of pixels,wherein the pixel signal readout section includes the analog-to-digital (AD) converter according to claim 12,wherein the analog-to-digital (AD) converter is disposed to correspond to a column array of pixels so as to convert a readout analog signal to a digital signal. 14. A camera system comprising: the solid-state imaging device according to claim 13; andan optical system that forms a subject image in the solid-state imaging device. 15. A binary conversion circuit comprising: a latch circuit configured to receive a clock signal and an output signal, and latch phase information of the clock signal when a level of the output signal is inverted;a conversion circuit configured to receive the latched phase information from the latch circuit and a pulse signal, and convert the latched phase information to a pulse train in response to the pulse signal; anda ripple counter section configured to receive the pulse train as a count clock and convert the phase information of the clock signal to a binary code by using the pulse train as a count clock,wherein the conversion circuit includes a first conversion circuit and a second conversion circuit,wherein the ripple counter section includes a first ripple counter section and a second ripple counter section,wherein the latch circuit includes four T-type flip-flops that latch different four clock signals, respectively, in which three consecutive T-type flip-flops form a first latch, and a remaining one of the four T-type flip-flops forms a second latch,wherein the binary conversion circuit further includes a selector that selects latched phase information of the three T-type flip-flops serving as the first latch of the latch circuit in response to a select signal, anda mask circuit that performs mask processing for determining whether or not latched phase information of the T-type flip-flop serving as the second latch of the latch circuit will be input to the second conversion circuit in response to a mask signal,wherein the first conversion circuit converts the four pieces of latched phase information of the latch circuit to a pulse train in response to a first pulse signal and outputs the converted signal as a count clock of the first ripple counter section; andwherein the second conversion circuit converts an output signal of the first ripple counter section or the latched phase information of the T-type flip-flop serving as the second latch, supplied via the mask circuit, to a count clock in response to a second pulse signal and outputs the count clock to the second ripple counter section that counts an upper bit. 16. The binary conversion circuit according to claim 15, wherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “0” and “4,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 0 to 7, the decimal numbers being used as the number of pulses. 17. A binary conversion circuit comprising: a latch circuit configured to receive a clock signal and an output signal, and latch phase information of the clock signal when a level of the output signal is inverted;a conversion circuit configured to receive the latched phase information from the latch circuit and a pulse signal, and convert the latched phase information to a pulse train in response to the pulse signal; anda ripple counter section configured to receive the pulse train as a count clock and convert the phase information of the clock signal to a binary code by using the pulse train as a count clock,wherein the latch circuit includes four T-type flip-flops that latch different four clock signals, respectively, in which three consecutive T-type flip-flops form a first latch, and a remaining one of the four T-type flip-flops forms a second latch,wherein the binary conversion circuit further includes a selector that selects latched phase information of the three T-type flip-flops serving as the first latch of the latch circuit in response to a select signal, andwherein the first conversion circuit converts the four pieces of latched phase information of the latch circuit to a pulse train in response to first and second pulse signals and outputs the converted signal as a count clock of the ripple counter section. 18. The binary conversion circuit according to claim 17, wherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “1” and “2,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 1 to 8, the decimal numbers being used as the number of pulses. 19. A binary conversion method comprising the steps of: latching phase information of a clock signal when the level of an output signal is inverted;converting the latched phase information to a pulse train in response to a pulse signal; andconverting the phase information to a binary value by using the pulse train as a count clock,wherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “0” and “4,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 0 to 7, the decimal numbers being used as the number of pulses, orwherein when a 4-bit BCD code is expressed by eight states 1000, 1100, 1110, 1111, 0111, 0011, 0001, and 0000, new eight states are formed from the initial eight states in such a way that most significant bit (MSB) values “1” and “0” are converted to “1” and “2,” respectively, and lower bit values “0” and “1” other than the MSB are converted to “0” and “1,” respectively, as they are, and BCD code values of the new eight states are added to obtain decimal numbers ranging between 1 to 8, the decimal numbers being used as the number of pulses. 20. The binary conversion method according to claim 19, wherein the phase information is converted to a plurality of pulse trains corresponding to a corresponding binary code. 21. The binary conversion method according to claim 19, wherein the phase information of one clock is latched at a plurality of timings, andwherein the latched phase information of each clock is converted to a pulse train. 22. The binary conversion method according to claim 21, wherein the phase information is converted to a plurality of pulse trains corresponding to a corresponding binary code.
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