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Semiconductor circuit structure and method of making the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
  • H01L-021/31
출원번호 US-0847374 (2010-07-30)
등록번호 US-8455978 (2013-06-04)
발명자 / 주소
  • Lee, Sang-Yun
출원인 / 주소
  • Lee, Sang-Yun
대리인 / 주소
    Martinez, Greg L.
인용정보 피인용 횟수 : 0  인용 특허 : 61

초록

A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region

대표청구항

1. A semiconductor structure, comprising: a support substrate which carries an electronic device;an interconnect region carried by the support substrate, the interconnect region including a conductive line connected to the electronic device;a semiconductor material region;a conductive bonding region

이 특허에 인용된 특허 (61)

  1. Kub Francis J. ; Temple Victor ; Hobart Karl ; Neilson John, Advanced methods for making semiconductor devices by low temperature direct bonding.
  2. Bhakta, Jayesh R.; Pauley, Jr., Robert S., Arrangement of integrated circuits in a memory module.
  3. Amir, Dudi, Electronic circuit board manufacturing process and associated apparatus.
  4. Lee, Sang Yun, Electronic circuit with embedded memory.
  5. Aronowitz Sheldon ; Puchner Helmut ; Kapre Ravindra A. ; Kimball James P., Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of sil.
  6. Leung Wingyu (Cupertino CA), High density SRAM circuit with ratio independent memory cells.
  7. Leung Wingyu (Cupertino CA) Hsu Fu-Chieh (Saratoga CA), High density SRAM circuit with single-ended memory cells.
  8. Kanatsu, Tomotoshi, Image processing apparatus and image processing method capable of executing high-performance processing without transmitting a large amount of image data to outside of the image processing apparatus during the processing.
  9. Fitch Jon T. (Austin TX) Venkatesan Suresh (Austin TX) Witek Keith E. (Austin TX), Integrated circuit having both vertical and horizontal devices and process for making the same.
  10. Sundahl, Robert C.; Wong, Kenneth, Interconnected circuit board assembly and system.
  11. Ouyang, Qiqing Christine; Chu, Jack Oon, Low leakage heterojunction vertical transistors and high performance devices thereof.
  12. Tiwari, Sandip, Low temperature semiconductor layering and three-dimensional electronic circuits using the layering.
  13. Geusic, Joseph E., Low temperature silicon wafer bond process with bulk material bond strength.
  14. Jolin, Edward M.; Delino, Julius, Memory module and computer system comprising a memory module.
  15. Miyasaka, Yoshio, Metal oxide layer having oxygen deficit tilting structure.
  16. Nakamura, Kuniyasu; Kakibayashi, Hiroshi; Ichihashi, Mikio; Isakozawa, Shigeto; Sato, Yuji; Hashimoto, Takahito, Method and apparatus for scanning transmission electron microscopy.
  17. Nakamura, Kuniyasu; Kakibayashi, Hiroshi; Ichihashi, Mikio; Isakozawa, Shigeto; Sato, Yuji; Hashimoto, Takahito, Method and apparatus for scanning transmission electron microscopy.
  18. Leung Wingyu ; Hsu Fu-Chieh, Method and structure for implementing a cache memory using a DRAM array.
  19. Kutz, Harold; Snyder, Warren, Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller.
  20. Lee,Sang Yun, Method for making a three-dimensional integrated circuit structure.
  21. Chan Kevin Kok ; D'Emic Christopher Peter ; Jones Erin Catherine ; Solomon Paul Michael ; Tiwari Sandip, Method for making bonded metal back-plane substrates.
  22. Ito Tatsuo (Joetsu JPX) Uchiyama Atsuo (Chiisagata JPX) Fukami Masao (Nagano JPX), Method for preparing a substrate for semiconductor devices.
  23. Brian S. Doyle, Method of delaminating a thin film using non-thermal techniques.
  24. Aspar Bernard,FRX ; Biasse Beatrice,FRX ; Bruel Michel,FRX, Method of obtaining a thin film of semiconductor material.
  25. Okihara Masao,JPX, Method of preparing a plan-view sample of an integrated circuit for transmission electron microscopy, and methods of obs.
  26. Hayashi Yoshihiro (Tokyo JPX), Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit.
  27. Tsai Hsi-Jung,TWX, Microcontroller with programmable embedded flash memory.
  28. Shigeeda Akio, Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory.
  29. Cleeves, James M.; Subramanian, Vivek, Multigate semiconductor device with vertical channel current and method of fabrication.
  30. Wahlstrom Sven E. (570 Jackson Dr. Palo Alto CA 94303), Multilevel integrated circuits employing fused oxide layers.
  31. Hsien, Kuo Chih, Personal computer main board for mounting therein memory module.
  32. Kiyofumi Sakaguchi JP; Kazutaka Yanagita JP, Porous region removing method and semiconductor substrate manufacturing method.
  33. Curran Patrick A. (Plano TX), Process for making a buried conductor by fusing two wafers.
  34. Takao Yoshihiro (Kawasaki JPX), Process for manufacturing three dimensional IC\s.
  35. Kaga Toru (Saitama JPX) Kawamoto Yoshifumi (Kanagawa JPX) Sunami Hideo (Tokyo JPX), Process for manufacturing vertical dynamic random access memories.
  36. Yamagata Kenji (Kawasaki JPX) Yonehara Takao (Atsugi JPX), Process for producing a semiconductor substrate.
  37. Yamagata Kenji,JPX ; Yonehara Takao,JPX, Process for producing a semiconductor substrate.
  38. Sakaguchi, Kiyofumi; Yonehara, Takao; Nishida, Shoji; Yamagata, Kenji, Process for producing semiconductor article.
  39. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  40. Grunewald,Wolfgang, Sample preparation for transmission electron microscopy.
  41. Lee, Sang-Yun, Semiconductor bonding and layer transfer method.
  42. Nemati Farid ; Plummer James D., Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches.
  43. Saito Keishi (Nabari JPX) Fujioka Yasushi (Ueno JPX), Semiconductor device having a semiconductor region in which a band gap being continuously graded.
  44. Lee, Sang-Yun, Semiconductor layer structure and method of making the same.
  45. Lee,Sang Yun, Semiconductor layer structure and method of making the same.
  46. Mazur Carlos A. (Austin TX) Fitch Jon T. (Austin TX) Hayden James D. (Austin TX) Witek Keith E. (Austin TX), Semiconductor memory device and method of formation.
  47. Sugahara Kazuyuki (Hyogo JPX) Ajika Natsuo (Hyogo JPX) Ogawa Toshiaki (Hyogo JPX) Iwamatsu Toshiaki (Hyogo JPX) Ipposhi Takashi (Hyogo JPX), Stacked-type semiconductor device.
  48. Takahashi Hiroyuki,JPX, Static random access memory (SRAM) circuit.
  49. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  50. Billon Thierry,FRX, Structure with a micro-electronic component made of a semi-conductor material difficult to etch and with metallized holes.
  51. Leedy Glenn J., Three dimensional structure memory.
  52. Kato Takashi (Sagamihara JPX) Taguchi Masao (Sagamihara JPX), Three-dimensional integrated circuit and manufacturing method thereof.
  53. Matsushita Takeshi,JPX, Three-dimensional integrated circuit device and its manufacturing method.
  54. Greenlaw, David, Three-dimensional integrated semiconductor devices.
  55. Zhang Guobiao, Three-dimensional read-only memory.
  56. Nemati,Farid; Yang,Kevin J., Thyristor-based memory and its method of operation.
  57. Noble Wendell P., Trench dram cell with vertical device and buried word lines.
  58. Hsu Chen-Chung (Taichung TWX), Trench method for three dimensional chip connecting during IC fabrication.
  59. Holloway Thomas C., Variable threshold voltage gate electrode for higher performance mosfets.
  60. Lee, Sang Yun, Wafer bonding method.
  61. Lee,Sang Yun, Wafer bonding method.
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