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Multi-layer interconnect structure for stacked dies 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/4763
출원번호 US-0750100 (2010-03-30)
등록번호 US-8466059 (2013-06-18)
발명자 / 주소
  • Chang, Hung-Pin
  • Chiu, Chien-Ming
  • Wu, Tsang-Jiuh
  • Shue, Shau-Lin
  • Yu, Chen-Hua
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Slater & Matsil, L.L.P.
인용정보 피인용 횟수 : 16  인용 특허 : 58

초록

A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconduct

대표청구항

1. A method of forming a semiconductor device, the method comprising: providing a first substrate, the first substrate having a through-substrate via extending from a first side into the first substrate;exposing the through-substrate via on a second side of the first substrate, the through-substrate

이 특허에 인용된 특허 (58)

  1. Chen,Chien Hua; Chen,Zhizhang; Meyer,Neal W., 3D interconnect with protruding contacts.
  2. Chiou, Wen-Chih; Wu, Weng-Jin, Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips.
  3. Matsui,Satoshi, Chip and multi-chip semiconductor device using thereof and method for manufacturing same.
  4. Pogge, H. Bernhard; Yu, Roy; Prasad, Chandrika; Narayan, Chandrasekhar, Chip and wafer integration process using vertical connections.
  5. Agarwala,Birendra N.; Coker,Eric M.; Correale, Jr.,Anthony; Rathore,Hazara S.; Sullivan,Timothy D.; Wachnik,Richard A., Dual-damascene metallization interconnection.
  6. Chiu, Ming-Yen; Chen, Hsien-Wei; Chen, Ming-Fa; Jeng, Shin-Puu, Dummy pattern in wafer backside routing.
  7. Chanchani,Rajen, Heterogeneously integrated microsystem-on-a-chip.
  8. Chudzik, Michael Patrick; Dennard, Robert H.; Divakaruni, Rama; Furman, Bruce Kenneth; Jammy, Rajarao; Narayan, Chandrasekhar; Purushothaman, Sampath; Shepard, Jr., Joseph F.; Topol, Anna Wanda, High density chip carrier with integrated passive devices.
  9. Chudzik,Michael Patrick; Dennard,Robert H.; Divakaruni,Rama; Furman,Bruce Kenneth; Jammy,Rajarao; Narayan,Chandrasekhar; Purushothaman,Sampath; Shepard, Jr.,Joseph F.; Topol,Anna Wanda, High density chip carrier with integrated passive devices.
  10. West, Jeffrey Alan; Simmons-Matthews, Margaret Rose; Amagai, Masazumi, IC having TSV arrays with reduced TSV induced stress.
  11. Siniaguine, Oleg, Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate.
  12. Siniaguine Oleg, Integrated circuits and methods for their fabrication.
  13. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  14. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  15. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  16. Savastiouk,Sergey; Halahan,Patrick B.; Kao,Sam, Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities.
  17. Tadatomo Suga JP, Interconnect structure for stacked semiconductor device.
  18. Patti, Robert, Interlocking conductor method for bonding wafers to produce stacked integrated circuits.
  19. Matsui,Kuniyasu, Intermediate chip module, semiconductor device, circuit board, and electronic device.
  20. Eilert,Sean S., Method and apparatus for generating a device ID for stacked devices.
  21. Valluri R. Rao ; Jeffrey K. Greason ; Richard H. Livengood, Method for distributing a clock on the silicon backside of an integrated circuit.
  22. Black Charles Thomas ; Burghartz Joachim Norbert ; Tiwari Sandip ; Welser Jeffrey John, Method for making three dimensional circuit integration.
  23. Tadatomo Suga JP, Method for manufacturing an interconnect structure for stacked semiconductor device.
  24. Soejima, Koji; Kawano, Masaya, Method for manufacturing semiconductor device.
  25. Komai, Naoki; Nakamura, Takuya, Method for manufacturing semiconductor device and semiconductor device.
  26. Beyne, Eric; Labie, Riet, Method for producing electrical through hole interconnects and devices made thereof.
  27. Gaul Stephen Joseph (Melbourne FL), Method of bonding wafers having vias including conductive material.
  28. Redwine Donald J. (Houston TX), Method of interconnect in an integrated circuit.
  29. Jackson, Timothy L.; Murphy, Tim E., Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof.
  30. Morrow, Patrick; List, R. Scott; Kim, Sarah E., Methods of forming backside connections on a wafer stack.
  31. Akram, Salman; Rigg, Sidney B., Methods of forming blind wafer interconnects.
  32. Thomas,Jochen; Schoenfeld,Olaf, Multi-chip device and method for producing a multi-chip device.
  33. Farnworth, Warren M.; Wood, Alan G.; Hiatt, William M.; Wark, James M.; Hembree, David R.; Kirby, Kyle K.; Benson, Pete A., Multi-dice chip scale semiconductor components and wafer level methods of fabrication.
  34. Gilmour Richard J. (Liberty Hill TX) Schrottke Gustav (Austin TX), Multiprocessor module packaging.
  35. Siniaguine Oleg ; Savastiouk Sergey, Package of integrated circuits and vertical integration.
  36. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.
  37. Savastiouk,Sergey; Halahan,Patrick B.; Kao,Sam, Packaging substrates for integrated circuits and soldering methods.
  38. Sailesh Chittipeddi ; William Thomas Cochran ; Yehuda Smooha, Process for forming a dual damascene bond pad structure over active circuitry.
  39. Bertagnolli Emmerich,DEX ; Klose Helmut,DEX, Process for producing semiconductor components between which contact is made vertically.
  40. Finnila Ronald M. (Carlsbad CA), Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substr.
  41. Kim,Sarah E.; List,R. Scott; Kellar,Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
  42. Mawatari, Kazuaki; Aoya, Kengo; Umeda, Yoshikatsu; West, Jeffrey A., Protruding TSV tips for enhanced heat dissipation for IC devices.
  43. Chen, Jung-Tai; Ho, Tzong-Che; Chu, Chun-Hsun, Self-aligned wafer or chip structure, and self-aligned stacked structure.
  44. Miyazawa, Ikuya; Ikehara, Tadayoshi, Semiconductor device and a method of manufacturing the same, a circuit board and an electronic apparatus.
  45. Akiyama, Kazutaka, Semiconductor device and method for manufacturing the same.
  46. Lin, Yaojian; Fang, Jianmin; Chen, Kang; Cao, Haijing, Semiconductor device and method of forming high-frequency circuit structure and method thereof.
  47. Myeong-cheol Kim KR; Hee-sung Yang KR, Semiconductor device having a conductive layer side surface slope which is at least 90.degree. and method for manufacturing the same.
  48. Iwasaki Ritsuko,JPX, Semiconductor device having an improved through-hole structure.
  49. Matsuki, Takeo; Takaishi, Yoshihiro, Semiconductor device structure and method for manufacturing the same.
  50. Jackson, Timothy L.; Murphy, Tim E., Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies.
  51. Jackson,Timothy L.; Murphy,Tim E., Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods.
  52. Patrick B. Halahan ; Oleg Siniaguine, Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same.
  53. Kirby, Kyle; Parekh, Kunal, Semiconductor with through-substrate interconnect.
  54. Fey,Kate E.; Byers,Charles L.; Mandell,Lee J., Space-saving packaging of electronic circuits.
  55. Chao, Clinton; Yuan, Tsorng Dih; Pan, Hsin Yu; Chen, Kim; Peng, Mark Shane; Karta, Tjandra Winata, Stacked structures and methods of fabricating stacked structures.
  56. Kong, Sik On, Three dimensional IC package module.
  57. Rumer, Christopher L.; Zarbock, Edward A., Through silicon via, folded flex microelectronic package.
  58. Akram,Salman; Watkins,Charles; Hiatt,Mark; Hembree,David; Wark,James; Farnworth,Warren; Tuttle,Mark; Rigg,Sidney; Oliver,Steven; Kirby,Kyle; Wood,Alan; Velicky,Lu, Through-wafer interconnects for photoimager and memory wafers.

이 특허를 인용한 특허 (16)

  1. Chang, Hung-Pin; Hsu, Kuo-Ching; Chen, Chen-Shien; Chiou, Wen-Chih; Yu, Chen-Hua, Bump structure for stacked dies.
  2. Choi, Ju-il; Fujisaki, Atsushi; Park, Byung-Iyul; Park, Ji-soon; Jang, Joo-hee; Jin, Jeong-gi, Integrated circuit devices having through-silicon vias and methods of manufacturing such devices.
  3. Chang, Hung-Pin; Hsu, Kuo-Ching; Chen, Chen-Shien; Chiou, Wen-Chih; Yu, Chen-Hua, Isolation structure for stacked dies.
  4. Hu, Dyi-Chung, Metal via structure.
  5. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Method for producing a protective structure.
  6. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Method for through silicon via structure.
  7. Chang, Hung-Pin; Chiu, Chien-Ming; Wu, Tsang-Jiuh; Shue, Shau-Lin; Yu, Chen-Hua, Multi-layer interconnect structure for stacked dies.
  8. Tsai, Cheng-Chun; Chang, Hung-Pin; Yang, Ku-Feng; Chen, Yi-Hsiu; Chiou, Wen-Chih, Semiconductor device and method.
  9. Farooq, Mukta G.; Graves-Abe, Troy L.; Landers, William F.; Petrarca, Kevin S.; Volant, Richard P., TSV pillar as an interconnecting structure.
  10. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Through silicon via structure.
  11. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Through silicon via structure.
  12. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Through silicon via structure.
  13. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
  14. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
  15. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
  16. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
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