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Semiconductor device and method for manufacturing the same

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/12
  • H01L-021/30
출원번호 US-0251641 (2011-10-03)
등록번호 US-8470688 (2013-06-25)
우선권정보 JP-2007-181762 (2007-07-11)
발명자 / 주소
  • Isobe, Atsuo
출원인 / 주소
  • Semiconductor Energy Laboratory Co., Ltd.
대리인 / 주소
    Robinson, Eric J.
인용정보 피인용 횟수 : 5  인용 특허 : 40

초록

A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate in

대표청구항

1. A method for manufacturing a semiconductor device comprising the steps of: forming a first damaged region in a first single-crystal semiconductor substrate;bonding the first single-crystal semiconductor substrate and a substrate having an insulating surface with a bonding layer interposed therebe

이 특허에 인용된 특허 (40)

  1. Bae, Geum-jong; Choe, Tae-hee; Kim, Sang-su; Rhee, Hwa-sung; Lee, Nae-in; Lee, Kyung-wook, CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same.
  2. Bae, Geum-jong; Choe, Tae-hee; Kim, Sang-su; Rhee, Hwa-sung; Lee, Nae-in; Lee, Kyung-wook, CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same.
  3. Bae, Geum-jong; Choe, Tae-hee; Kim, Sang-su; Rhee, Hwa-sung; Lee, Nae-in; Lee, Kyung-wook, CMOS integrated circuit devices and substrates having unstrained silicon active layers.
  4. Shunpei Yamazaki JP; Jun Koyama JP; Yoshiharu Hirakata JP; Takeshi Fukunaga JP, Electrooptical device.
  5. Yamazaki, Shunpei; Koyama, Jun; Hirakata, Yoshiharu; Fukunaga, Takeshi, Electrooptical device.
  6. Yamazaki, Shunpei; Koyama, Jun; Hirakata, Yoshiharu; Fukunaga, Takeshi, Electrooptical device.
  7. Yamazaki,Shunpei; Koyama,Jun; Hirakata,Yoshiharu; Fukunaga,Takeshi, Electrooptical device.
  8. Yamazaki,Shunpei; Takayama,Toru; Akiba,Mai, Light emitting device and method of manufacturing the same.
  9. Takayama, Toru; Arai, Yasuyuki, Method for peeling off semiconductor element and method for manufacturing semiconductor device.
  10. Takayama,Toru; Arai,Yasuyuki, Method for peeling off semiconductor element and method for manufacturing semiconductor device.
  11. Shunpei Yamazaki JP; Hisashi Ohtani JP, Method of fabricating a high reliable SOI substrate.
  12. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
  13. Yamazaki,Shunpei; Ohtani,Hisashi, Method of fabricating a semiconductor device.
  14. Yamazaki,Shunpei; Ohtani,Hisashi, Method of fabricating a semiconductor device.
  15. Cederbaum Carl (Paris FRX) Chanclou Roland (Perthes FRX) Combes Myriam (Evry FRX) Mon Patrick (Ponthierry FRX), Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom.
  16. Inoue Shunsuke,JPX ; Miyawaki Mamoru,JPX ; Kohchi Tetsunobu,JPX, Method of making a semiconductor device.
  17. Nakamura Mitsuyoshi,JPX, Method of manufacturing a semiconductor device.
  18. Shunpei Yamazaki JP, Method of manufacturing a semiconductor device.
  19. Yamazaki,Shunpei, Method of manufacturing a semiconductor device.
  20. Bae,Geum jong; Choe,Tae hee; Kim,Sang su; Rhee,Hwa sung; Lee,Nae in; Lee,Kyung wook, Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein.
  21. Yu Bin, Multiple active layer integrated circuit and a method of making such a circuit.
  22. Yamazaki, Shunpei, Nonvolatile memory and electronic apparatus.
  23. Yamazaki, Shunpei, Nonvolatile memory and electronic apparatus.
  24. Kirsch Howard C. (Austin TX), Plural transistor silicon on insulator structure with shared electrodes.
  25. Fukunaga Takeshi,JPX, Process for production of SOI substrate and process for production of semiconductor device.
  26. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
  27. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
  28. Fukunaga,Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
  29. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.
  30. Yamazaki,Shunpei; Takayama,Toru; Maruyama,Junya; Ohno,Yumiko, Semiconductor chip and method for manufacturing the same.
  31. Yamazaki,Shunpei; Takayama,Toru; Maruyama,Junya; Ohno,Yumiko, Semiconductor chip and method manufacturing the same.
  32. Nakamura Mitsuyoshi,JPX, Semiconductor device and method of manufacturing the same.
  33. Kato,Kiyoshi; Takayama,Toru; Maruyama,Junya; Goto,Yuugo; Ohno,Yumiko, Semiconductor device comprising a light emitting element and a light receiving element.
  34. Yamazaki Shunpei,JPX ; Ohtani Hisashi,JPX ; Koyama Jun,JPX ; Fukunaga Takeshi,JPX, Semiconductor device having an SOI structure and manufacturing method therefor.
  35. Yamazaki,Shunpei; Ohtani,Hisashi; Hiroki,Masaaki; Tanaka,Koichiro; Shiga,Aiko; Akiba,Mai, Semiconductror fabricating apparatus.
  36. Kuriyama Hirotada (Hyogo JPX), Static random access type semiconductor memory device.
  37. Bansal, Jai P.; Bertin, Claude L.; Troutman, Ronald R., Structure of stacked, complementary MOS field effect transistor circuits.
  38. Pfiester James R. (Austin TX), Thin-film transistor having an inlaid thin-film channel region.
  39. Chan, Victor; Guarini, Kathryn W.; Ieong, Meikei, Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers.
  40. Kadosh Daniel ; Gardner Mark I. ; Duane Michael, Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in rel.

이 특허를 인용한 특허 (5)

  1. Cao, Jianjun; Beach, Robert; Lidow, Alexander; Nakata, Alana; Zhao, Guangyuan; Ma, Yanping; Strittmatter, Robert; De Rooij, Michael A.; Zhou, Chunhua; Kolluri, Seshadri; Liu, Fang-Chang; Chiang, Ming-Kun; Cao, Jiali; Jauhar, Agus, GaN transistors with polysilicon layers used for creating additional components.
  2. Oxland, Richard Kenneth; Dal, Mark van, Nickelide source/drain structures for CMOS transistors.
  3. Yoneda, Seiichi, Semiconductor device and display device including the same.
  4. Yamazaki, Shunpei; Koyama, Jun, Semiconductor memory device including stacked sub memory cells.
  5. Yamazaki, Shunpei; Koyama, Jun, Semiconductor memory device including stacked sub memory cells.
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