초록 ▼

An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified out

An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.

대표청구항 ▼

1. An amplifier comprising: an input stage having an input for receiving an input signal, and an output; andan output stage having an input coupled to said output of said input stage, and an output for providing an amplified output signal,wherein said output stage comprises:a gain stage having an in

1. An amplifier comprising: an input stage having an input for receiving an input signal, and an output; andan output stage having an input coupled to said output of said input stage, and an output for providing an amplified output signal,wherein said output stage comprises:a gain stage having an input forming said input of said output stage, an output for providing said amplified output signal, and first and second bias terminals,wherein said gain stage comprises: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode forming a first differential input terminal of said gain stage, and a second current electrode coupled to said output of said gain stage;a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode forming a second differential input terminal of said gain stage, and a second current electrode coupled to a second power supply voltage terminal;a third transistor having a first current electrode coupled to said control electrode of said first transistor, a control electrode forming said first bias terminal of said gain stage, and a second current; anda fourth transistor having a first current, a control electrode forming a second bias terminal of said gain stage, and a second current electrode coupled to said control electrode of said second transistor; anda bias circuit having a first and second output terminals coupled to said first and second bias terminals of said gain stage, wherein during a turn-on period said bias circuit gradually ramps said first and second bias terminals from respective first and second initial voltages to respective first and second bias voltages. 2. The amplifier of claim 1 wherein during a turn-off period, said bias circuit gradually ramps said first and second bias terminals of said gain stage from said respective first and second bias voltages to said respective first and second initial voltages. 3. The amplifier of claim 1 wherein said input stage comprises: a voltage gain stage having an input terminal for receiving said input signal, and an output terminal; anda transconductance stage having an input terminal coupled to said output terminal of said voltage gain stage, and an output terminal coupled to said input of said output stage. 4. The amplifier of claim 1 wherein said first and third transistors comprise P-channel MOS transistors, and said second and fourth transistors comprise N-channel MOS transistors. 5. An audio amplifier comprising: a voltage gain stage having an input terminal for receiving an audio input signal, and an output terminal;a transconductance stage having an input terminal selectively coupled to said output terminal of said voltage gain stage, a first output terminal, and a second output terminal; anda class AB output stage having a first and second input terminals respectively coupled to said first and second output terminals of said transconductance stage, first and second bias terminals, and an output terminal for providing an amplified audio output signal, wherein said class AB output stage is inoperative when a voltage at first and second bias terminals are at first and second initial voltages, and said class AB output stage clamps voltages at said first and second input terminals to respective clamp voltages when said first and second bias terminals are equal to first and second bias voltages, respectively, and comprising a bias circuit for gradually ramping said first and second bias terminals from corresponding initial voltages to corresponding bias voltages. 6. The audio amplifier of claim 5 further comprising a clock generator circuit having an input terminal for receiving an ON signal, and output terminals coupled to said bias circuit and responsive to said ON signal for defining a plurality of phases of the audio amplifier. 7. The audio amplifier of claim 6 wherein said clock generator defines a first phase of the audio amplifier for biasing first and second terminals of a first capacitor to a first reference voltage and coupling said output terminal of said class AB output stage to the input terminal of said voltage gain stage. 8. The audio amplifier of claim 7 wherein said clock generator defines a second phase subsequent to said first phase during which said bias circuit gradually ramps said first and second bias terminals from said corresponding initial voltages to said corresponding bias voltages. 9. The audio amplifier of claim 8 wherein during said second phase said clock generator couples said first capacitor between said output terminal of said class AB output stage and said input terminal of said transconductance stage. 10. The audio amplifier of claim 8 wherein said bias circuit further comprises a ramp detection circuit for detecting that said first and second bias terminals are both substantially at said respective first and second bias voltages, and providing an OK signal in response thereto. 11. The audio amplifier of claim 10 wherein during a third phase subsequent to said second phase said clock generator couples said output terminal of said voltage gain stage to said input terminal of said transconductance stage. 12. The audio amplifier of claim 11 wherein during a fourth phase subsequent to said third phase said clock generator decouples said output terminal of said class AB output stage from said input terminal of said voltage gain stage. 13. The audio amplifier of claim 12 wherein during said fourth phase said clock generator gradually decouples said output terminal of said class AB output stage from said input terminal of said voltage gain stage. 14. A method of turning on an audio amplifier having a class AB output stage to reduce audible transients comprising: biasing a first output transistor to be nonconductive in response to a first bias signal being at a first initial voltage, and to provide a voltage to an output terminal of the class AB output stage proportional to a voltage received at a control electrode thereof in response to said first bias signal being at a first bias voltage;biasing a second output transistor to be nonconductive in response to a second bias signal being at a second initial voltage, and to provide a voltage to said output terminal of the class AB output stage proportional to a voltage received at a control electrode thereof in response to said second bias signal being at a second bias voltage;gradually ramping said first bias signal from said first initial voltage to said first bias voltage;gradually ramping said second bias signal from said second initial voltage to said second bias voltage; andsubsequently enabling an operation of the audio amplifier. 15. The method of claim 14 further comprising: biasing first and second terminals of a first capacitor to a first reference voltage and coupling an output terminal of the audio amplifier to an input terminal of the audio amplifier during a first phase of the audio amplifier. 16. The method of claim 15 further comprising: coupling said output terminal of the audio amplifier to said input terminal of the audio amplifier and to a reference voltage terminal during said first phase of the audio amplifier. 17. The method of claim 16 wherein: gradually ramping said first and second bias signals from said first and second initial voltages, respectively, to said first and second bias voltages, respectively, during a second phase subsequent to said first phase. 18. The method of claim 17 further comprising: detecting that said first and second bias terminals are both substantially at said first and second bias voltages, respectively, and initiating a third phase subsequent to said second phase in response thereto. 19. The method of claim 18 further comprising: decoupling said output terminal of the audio amplifier from said reference voltage terminal during said third phase. 20. The method of claim 19 further comprising: decoupling said output terminal of the audio amplifier from said input terminal of the audio amplifier during a fourth phase subsequent to said third phase. 21. The method of claim 20 wherein said decoupling said output terminal of the audio amplifier from said input terminal of the audio amplifier comprises: gradually decoupling said output terminal of the audio amplifier from said input terminal of the audio amplifier during said fourth phase. 22. The amplifier of claim 1 wherein: said second current electrode of said third transistor is coupled to said control electrode of said second transistor; andsaid first current electrode of said fourth transistor is coupled to said control electrode of said first transistor.