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Method and system for error correction in flash memory

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03M-013/00
출원번호 US-0946520 (2010-11-15)
등록번호 US-8473812 (2013-06-25)
발명자 / 주소
  • Ramamoorthy, Aditya
  • Wu, Zining
  • Sutardja, Pantas
출원인 / 주소
  • Marvell World Trade Ltd.
인용정보 피인용 횟수 : 29  인용 특허 : 22

초록

A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate a series of encoded data bits, and converts the series of encoded data bits into a series of data sy

대표청구항

1. A controller for a multi-level solid state non-volatile memory array having memory cells, the memory cells adapted to store data using a first number of digital levels, the controller configured to: encode a series of data bits to generate a series of encoded data bits;convert the series of encod

이 특허에 인용된 특허 (22)

  1. Li,Yan; Pham,Long, Apparatus for programming of multi-state non-volatile memory using smart verify.
  2. Masumoto, Masayuki; Kurata, Kazushi; Tsuruta, Hideyo, Decoding apparatus and encoding apparatus with specific bit sequence deletion and insertion.
  3. Denissen Adrianus J. M. (Groenewoudseweg 1 5621 BA Eindhoven NLX) Zwaans Bernardus A. M. (Groenewoudseweg 1 5621 BA Eindhoven NLX), Encoding/decoding circuit, and digital video system comprising the circuit.
  4. Hans-Werner Knefel DE, Error recognition in a storage system.
  5. Yoshida Hideo (Kanagawa JPX), Error-correction encoding and decoding system.
  6. You,Byoung Sung, Flash memory device with reduced access time.
  7. Eidson,Donald Brian; Krieger,Abraham; Murali,Ramaswamy, Iterative decoder employing multiple external code error checks to lower the error floor.
  8. Shinagawa,Chiaki; Kanamori,Motoki; Shiraishi,Atsushi, Memory card.
  9. Lester, Robert A.; MacLaren, John M.; Ferguson, Patrick L.; Larson, John E., Memory data verify operation.
  10. Takeuchi Ken,JPX ; Tanaka Tomoharu,JPX, Memory system.
  11. Horowitz,Mark A.; Best,Scott C.; Stonecypher,William F., Method and apparatus for multi-level signaling.
  12. Zaleski, II,Kenneth G; Hebsgaard,Anders, Method and apparatus for performing trellis coded modulation of signals for transmission on a TDMA channel of a cable network.
  13. Vafai Manouchehr ; Rostoker Michael D., Method and apparatus for significantly improving the reliability of multilevel memory architecture.
  14. Guterman,Daniel C.; Fong,Yupin Kawing, Multi-state memory.
  15. Tanzawa, Toru; Atsumi, Shigeru, Non-volatile semiconductor memory.
  16. Tanzawa, Toru; Atsumi, Shigeru, Non-volatile semiconductor memory.
  17. Kang, Hee Bok, Nonvolatile ferroelectric memory device and method for storing multiple bit using the same.
  18. Noda,Satoshi; Kozakai,Kenji; Matsushita,Toru; Jono,Yusuke, Nonvolatile memory and nonvolatile memory apparatus.
  19. Kubo,Kazuo; Yoshida,Hideo; Ichibangase,Hiroshi, Optical transmission system, fec multiplexer, fec multiplexer/separator, and error correction method.
  20. Micheloni, Rino; Losavio, Aldo, Self-repair method via ECC for nonvolatile memory devices, and relative nonvolatile memory device.
  21. Riho,Yoshiro; Ito,Yutaka, Semiconductor device and testing method for same.
  22. Kitayama Seishi (Tokyo JPX) Yato Fumihiro (Tokyo JPX) Kurematsu Akira (Tokyo JPX), Voice encoding and decoding device.

이 특허를 인용한 특허 (29)

  1. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W.; Jaser, Ihab, Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system.
  2. Marelli, Alessia; Micheloni, Rino, Background reference positioning and local reference positioning using threshold voltage shift read.
  3. Conway, Bruce; Halperin, Louis E., Data recovery utilizing optimized code table signaling.
  4. Conway, Bruce, Dynamic control of quality of service (QOS) using derived QOS measures.
  5. Conway, Bruce, Enhanced signal integrity and communication utilizing optimized code table signaling.
  6. Conway, Bruce, Enhanced signal integrity and communication utilizing optimized code table signaling.
  7. Sankaranarayanan, Sundararajan; Haratsch, Erich F., Framework for balancing robustness and latency during collection of statistics from soft reads.
  8. Sankaranarayanan, Sundararajan; Haratsch, Erich F., Framework for balancing robustness and latency during collection of statistics from soft reads.
  9. Micheloni, Rino; Marelli, Alessia; Norrie, Christopher I. W., High quality log likelihood ratios determined using two-index look-up table.
  10. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W., Layer specific LDPC decoder.
  11. Micheloni, Rino; Onufryk, Peter Z.; Marelli, Alessia; Norrie, Christopher I. W., Layer specific attenuation factor LDPC decoder.
  12. Mizushima, Nagamasa; Kawamura, Atsushi; Koseki, Hideyuki, Memory controller and data control method.
  13. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W.; Jaser, Ihab, Memory controller and integrated circuit device for correcting errors in data read from memory cells.
  14. Micheloni, Rino; Marelli, Alessia; Onufryk, Peter Z.; Norrie, Christopher I. W., Method and apparatus for layer-specific LDPC decoding.
  15. Brown, David Alan; Onufryk, Peter Z.; Talledo, Cesar, Method and apparatus for translated routing in an interconnect switch.
  16. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Method and apparatus with program suspend using test mode.
  17. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory controller and method for erase suspend management that increments the number of program and erase cycles after erase suspend.
  18. Micheloni, Rino; Aldarese, Antonio; Scommegna, Salvatrice, Nonvolatile memory system with erase suspend circuit and method for erase suspend management.
  19. Micheloni, Rino, Nonvolatile memory system with program step manager and method for program step management.
  20. Micheloni, Rino; Marelli, Alessia; Bates, Stephen, Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction.
  21. Conway, Bruce, Optimized code table signaling for authentication to a network and information system.
  22. Conway, Bruce, Optimized code table signaling for authentication to a network and information system.
  23. Conway, Bruce, Optimized code table signaling for authentication to a network and information system.
  24. Conway, Bruce, Optimized code table signaling for authentication to a network and information system.
  25. Conway, Bruce, Optimized code table signaling for authentication to a network and information system.
  26. Conway, Bruce, Optimized data transfer utilizing optimized code table signaling.
  27. Manning, Troy A.; Larsen, Troy D.; Culley, Martin L., Physical page, logical page, and codeword correspondence.
  28. Micheloni, Rino; Marelli, Alessia; Crippa, Luca, System and method for memory block pool wear leveling.
  29. Graumann, Peter John Waldemar; Fard, Saeed Fouladi, Variable T BCH encoding.
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