IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0418979
(2009-04-06)
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등록번호 |
US-8479133
(2013-07-02)
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발명자
/ 주소 |
- Wendling, Xavier
- Simkins, James M.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
167 |
초록
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According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter;
According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.
대표청구항
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1. A method of configuring a filter in a circuit to be implemented in an integrated circuit, the method comprising: receiving a high level design of the circuit;identifying a filter in the high level design;analyzing coefficients of the filter;transforming, using a computer, the filter of the high l
1. A method of configuring a filter in a circuit to be implemented in an integrated circuit, the method comprising: receiving a high level design of the circuit;identifying a filter in the high level design;analyzing coefficients of the filter;transforming, using a computer, the filter of the high level design to a symmetric transpose filter using a plurality of processing blocks, each processing block of the plurality of processing blocks configured to accommodate a common coefficient associated with the processing block, wherein the filter receives an input signal external to the filter at a first processing block and each processing block after the first processing block is configured to receive a different tap associated with the common coefficient for the processing block and the input signal directly at the processing block, and wherein the first processing block receives a highest order coefficient;implementing, for each processing block of the plurality of processing blocks, a pre-adder circuit having an adder/subtractor coupled to an output of a first logic gate and an output of a second logic gate;coupling, for each processing block of the plurality of processing blocks, control signals to the adder/subtractor, the first logic gate and the second logic gate;dynamically selecting, for each processing block of the plurality of processing blocks, whether the adder/subtractor operates as an adder or a subtractor based upon the control signals during operation of the integrated circuit; anddynamically selecting, for each processing block of the plurality of processing blocks, a register depth to an input port of the first logic gate based upon the control signals during operation of the integrated circuit;wherein a second input port of the first logic gate and a third input port of the second logic gate enable dynamic power gating of the pre-adder circuit to enable power conservation. 2. The method of claim 1 wherein transforming the filter of the high level design to a symmetric transpose filter using a plurality of processing blocks comprises configuring the filter as a symmetric transpose convolution filter. 3. The method of claim 1 wherein analyzing the coefficients comprises identifying symmetrical coefficients of the filter in the high level design. 4. The method of claim 1 further comprising providing the common coefficient as a first input to a multiplier of the processing block. 5. The method of claim 4 further comprising providing a sum of taps associated with the common coefficient as a second input to the multiplier. 6. The method of claim 5 wherein coupling the sum of the taps associated with the common coefficient as a second input to the multiplier comprises generating the sum using the pre-adder circuit of a DSP block. 7. The method of claim 4 further comprising providing a difference of taps associated with the common coefficient as a second input to the multiplier. 8. A computer program product comprising: a non-transitory computer-readable medium comprising computer-readable program code that transforms a circuit design to a placement configuration, the non-transitory computer-readable medium comprising: computer-readable program code that identifies a filter in a high level design;computer-readable program code that analyzes a coefficients of the filter; andcomputer-readable program code that configures the filter as a symmetric transpose filter using a plurality of processing blocks, each processing block of the plurality of processing blocks configured to accommodate a common coefficient associated with the processing block, wherein the filter receives an input signal external to the filter at a first processing block and each processing block after the first processing block is configured to receive a different tap associated with the common coefficient for the processing block and the input signal directly at the processing block, and wherein the first processing block receives a highest order coefficient;computer-readable program code that implements, for each processor processing block of the plurality of processing blocks, a pre-adder circuit having an adder/subtractor coupled to an output a first logic gate and an output of a second logic gate;computer-readable program code that enables coupling, for each processing block of the plurality of processing blocks, control signals to the adder/subtractor, the first logic gate and the second logic gate;computer-readable program code that enables dynamically selecting, for each processing block of the plurality of processing blocks, whether the adder/subtractor operates as an adder or a subtractor based upon the control signals during operation of an integrated circuit; andcomputer-readable program code that enables dynamically selecting, for each processing block of the plurality of processing blocks, a register depth to an input port of the first logic gate based upon the control signals during operation of the integrated circuit;wherein a second input port of the first logic gate and a third input port of the second logic gate provide dynamic power gating of the pre-adder circuit to enable power conservation. 9. The computer program product of claim 8 wherein the computer-readable program code that configures the filter as a symmetric transpose filter using a plurality of processing blocks comprises computer-readable program code that configures the filter as a symmetric transpose convolution filter. 10. The computer program product of claim 8 wherein the computer-readable program code that analyzes the coefficients of the filter comprises computer-readable program code that identifies symmetrical coefficients of the filter. 11. The computer program product of claim 8 further comprising computer-readable program code that provides the common coefficient as a first input to a multiplier of the processing block. 12. The computer program product of claim 11 further comprising computer-readable program code that provides a sum or difference of the taps associated with the common coefficient as a second input to the multiplier. 13. The computer program product of claim 12 wherein the computer-readable program code that provides the sum or difference of the taps associated with the common coefficient as a second input to the multiplier comprises computer-readable program code that generates the sum or difference using a pre-adder circuit of a DSP block. 14. The computer program product of claim 8 further comprising computer-readable program code that implements the symmetric transpose filter according to the placement configuration using circuit elements of the integrated circuit. 15. A circuit implementing a symmetric transpose filter in an integrated circuit, the circuit comprising: a plurality of processing blocks, each processing block having: a plurality of delay elements;a pre-adder circuit coupled to receive a first tap of the symmetric transpose filter by way of a first delay element of the plurality of delay elements and a second tap of the symmetric transpose filter by way of a second delay element of the plurality of delay elements, wherein the first tap and the second tap have a common coefficient, wherein the pre-adder circuit has an adder/subtractor coupled to an output of a first logic gate and an output of a second logic gate and is dynamically configured to operate as either an adder or a subtractor based upon control signals during operation of the integrated circuit; and wherein a register depth to an input port of the first logic gate is dynamically selected based upon the control signals during operation of the integrated circuit;a multiplier coupled to receive an output of the pre-adder circuit comprising a sum of the first tap and the second tap at a first input and the common coefficient at a second input; andan adder coupled to receive the output of the multiplier;wherein the symmetric transpose filter receives an input signal external to the symmetric transpose filter at a first processing block and each processing block of the plurality of processing blocks after the first processing block is configured to receive the input signal directly at the processing block and a different first tap, and wherein the first processing block receives a highest order coefficient; andwherein, for each processing block, a second input port of the first logic gate and a third input port of the second logic gate provide dynamic power gating of the pre-adder circuit to enable power conservation. 16. The circuit of claim 15 wherein the symmetric transpose filter comprises a transpose convolution filter. 17. The circuit of claim 15 wherein the common coefficient is associated with symmetrical coefficients of the symmetric transpose filter. 18. The circuit of claim 15 wherein the number of taps of the symmetric transpose filter comprises an even number of taps. 19. The circuit of claim 15 wherein the number of taps of the symmetric transpose filter comprises an odd number of taps and a subset of the odd number of taps is coupled to the pre-adder circuit. 20. The circuit of claim 15 wherein the plurality of delay elements, the pre-adder circuit and the multiplier are part of a digital signal processing block of the integrated circuit.
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