IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0563953
(2009-09-21)
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등록번호 |
US-8486771
(2013-07-16)
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발명자
/ 주소 |
- Letertre, Fabrice
- Faure, Bruce
- Krames, Michael R.
- Gardner, Nathan F.
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
31 |
초록
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Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant materia
Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods. Engineered substrates include a plurality of structures comprising a semiconductor material disposed on a layer of material exhibiting a changeable viscosity.
대표청구항
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1. A method of fabricating a semiconductor structure or device, comprising: forming a layer of semiconductor material over a base layer;affixing the layer of semiconductor material to a layer of compliant material;separating the layer of semiconductor material and the base layer;removing a portion o
1. A method of fabricating a semiconductor structure or device, comprising: forming a layer of semiconductor material over a base layer;affixing the layer of semiconductor material to a layer of compliant material;separating the layer of semiconductor material and the base layer;removing a portion of the layer of semiconductor material to expose regions of the layer of compliant material between each of a plurality of structures comprising the semiconductor material; anddepositing another layer of semiconductor material over the plurality of structures while altering a viscosity of the layer of compliant material. 2. The method of claim 1, further comprising applying a layer of dielectric material over the layer of semiconductor material. 3. The method of claim 1, wherein affixing the layer of semiconductor material to a layer of compliant material comprises bonding a layer of indium gallium nitride to a layer of material comprising at least one of a low temperature oxide, a phosphosilicate glass, a borosilicate, a borophosphosilicate glass, a polyimide, a siloxane spin-on-glass, an inorganic spin-on-glass, or a silicate to the layer of indium gallium nitride. 4. The method of claim 1, wherein depositing another layer of semiconductor material over the plurality of structures while altering a viscosity of the layer of compliant material comprises depositing the another layer of semiconductor material at a temperature at or above a glass transition temperature of the layer of compliant material. 5. The method of claim 4, wherein depositing the another layer of semiconductor material at a temperature at or above a glass transition temperature of the layer of compliant material comprises depositing indium gallium nitride at a temperature in a range of from about 600° C. to about 1150° C. 6. The method of claim 1, wherein depositing another layer of semiconductor material over the plurality of structures while altering a viscosity of the layer of compliant material comprises relaxing the semiconductor material within each of the structures of the plurality while maintaining separation therebetween. 7. The method of claim 1, further comprising forming the plurality of structures to comprise a III-V type semiconductor material. 8. The method of claim 1, further comprising forming the plurality of structures to comprise In0.10Ga0.90N and selecting the another layer of semiconductor material to comprise In0.25Ga0.75N. 9. The method of claim 1, wherein depositing another layer of semiconductor material comprises depositing a layer of indium gallium nitride having an increased critical thickness in comparison to a layer of indium gallium nitride formed on a conventional substrate. 10. A method of fabricating a semiconductor structure or device, comprising: forming an epitaxial layer of indium gallium nitride over a layer of borophosphosilicate glass;removing portions of the epitaxial layer of indium gallium nitride to form a plurality of openings therein; anddepositing another layer of indium gallium nitride over the epitaxial layer of indium gallium nitride at a temperature at or above a glass transition temperature of the layer of borophosphosilicate glass. 11. The method of claim 10, wherein depositing another layer of indium gallium nitride over the epitaxial layer of indium gallium nitride comprises depositing a layer of In0.25Ga0.75N over a layer of In0.1Ga0.9N. 12. The method of claim 10, wherein depositing another layer of indium gallium nitride over the epitaxial layer of indium gallium nitride at a temperature at or above a glass transition temperature of the layer of borophosphosilicate glass comprises depositing the another layer of indium gallium nitride over the epitaxial layer of indium gallium nitride at a temperature of about 600° C. or greater. 13. The method of claim 10, further comprising depositing a third layer of indium gallium nitride over the another layer of indium gallium nitride at a temperature at or above a glass transition temperature of the layer of borophosphosilicate glass. 14. A method of fabricating a semiconductor structure or device, comprising: forming a layer of III-V type semiconductor material on an intermediate material overlying a first substrate;attaching the layer of III-V type semiconductor material to a layer of material overlying a second substrate;removing the layer of III-V type semiconductor material from the first substrate after attaching the second substrate to the layer of III-V type semiconductor material;removing portions of the layer of III-V type semiconductor material to form a plurality of structures, each structure of the plurality being separated from adjacent structures by exposed regions of the layer of material; andheating the layer of material to decrease a viscosity thereof. 15. The method of claim 14, wherein forming a layer of III-V type semiconductor material on an intermediate material overlying a first substrate comprises depositing a layer of indium gallium nitride. 16. The method of claim 14, wherein attaching the layer of III-V type semiconductor material to the second substrate comprises bonding the layer of III-V semiconductor type material to the layer of material. 17. The method of claim 14, wherein removing the layer of III-V type semiconductor material from the first substrate comprises: implanting ions into at least one of the layer of III-V type semiconductor material and the first substrate to form an ion implant layer; anddelaminating the layer of III-V type semiconductor material from the first substrate along the ion implant layer. 18. The method of claim 14, further comprising selecting the layer of material to comprise a material capable of being reflowed. 19. The method of claim 14, wherein heating the layer of material to decrease a viscosity thereof comprises depositing another layer of III-V type semiconductor material over the plurality of structures at a temperature sufficient to reflow the layer of material. 20. The method of claim 19, wherein depositing another layer of III-V type semiconductor material over the plurality of structures at a temperature sufficient to reflow the layer of material comprises depositing In0.25Ga0.75N over a plurality of structures comprising In0.15Ga0.85N at a temperature in a range of from about 750° C. to about 1150° C. 21. The method of claim 19, wherein depositing another layer of III-V type semiconductor material over the plurality of structures at a temperature sufficient to reflow the layer of material comprises depositing InxGa1-xN over a plurality of structures comprising InyGa1-yN at a temperature in a range of from about 750° C. to about 1150° C., wherein x and y independently represent a number of between 0.01 and 0.15. 22. A method of forming an engineered substrate, comprising: growing an epitaxial layer of indium gallium nitride on a substrate;attaching the layer of indium gallium nitride to a layer of a flowable material overlying another substrate on a side thereof opposite the substrate;separating the substrate from the layer of indium gallium nitride;removing portions of the layer of indium gallium nitride to form a plurality of structures comprising indium gallium nitride; anddepositing another layer of indium gallium nitride at a temperature sufficient to reflow the layer of flowable material. 23. The method of claim 22, wherein growing an epitaxial layer of indium gallium nitride on a substrate comprises growing the epitaxial layer of indium gallium nitride on a layer of gallium nitride formed on the base material of the substrate. 24. The method of claim 22, wherein attaching the another substrate to the layer of indium gallium nitride comprises attaching the another substrate to a layer of material comprising at least one of a low temperature oxide, a phosphosilicate glass, a borosilicate, a borophosphosilicate glass, a polyimide, a siloxane spin-on-glass, an inorganic spin-on-glass, or a silicate to the layer of indium gallium nitride. 25. The method of claim 22, further comprising selecting the another layer of indium gallium nitride to comprise a higher percentage of indium than the layer of indium gallium nitride.
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