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Package for a power semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/495
출원번호 US-0928404 (2010-12-10)
등록번호 US-8487417 (2013-07-16)
발명자 / 주소
  • Balakrishnan, Balu
  • Hawthorne, Brad L.
  • Bäurle, Stefan
출원인 / 주소
  • Power Integrations, Inc.
대리인 / 주소
    The Law Offices of Bradley J. Bereznak
인용정보 피인용 횟수 : 1  인용 특허 : 82

초록

A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with re

대표청구항

1. A package for a semiconductor die comprising: a die attach pad providing an attachment surface area for the semiconductor die;a plurality of leads:one or more tie bars integrally connected to the die attach pad, the die attach pad being disposed in a first general plane and the one or more tie ba

이 특허에 인용된 특허 (82)

  1. Rumennik Vladimir (Los Altos CA) Grabowski Wayne B. (Mountain View CA), Bi-directional MOSFET switch.
  2. Gerbsch,Erich William; Taylor,Ralph S., Electrically isolated and thermally conductive double-sided pre-packaged component.
  3. Teratani Tatsuo (Aichi JPX), Electronic circuit assembly.
  4. Disney, Donald R., Electronic circuit control element with tap element.
  5. Disney,Donald Ray, Gate etch process for a high-voltage FET.
  6. Disney,Donald Ray, Gate etch process for a high-voltage FET.
  7. Parthasarathy,Vijay, Gate metal routing for transistor with checkerboarded layout.
  8. Parthasarathy, Vijay; Manley, Martin H., Gate pullback at ends of high-voltage vertical transistor structure.
  9. Ewer Peter R.,GBX ; Steers Mark,GBX, High current capacity semiconductor device housing.
  10. Eklund Klas H. (Sollentuna SEX), High voltage MOS transistor with a low on-resistance.
  11. Grabowski Wayne B. (Mountain View CA) Rumennik Vladimir (Los Altos CA), High voltage transistor.
  12. Disney, Donald Ray; Darwish, Mohamed, High-voltage lateral transistor with a multi-layered extended drain structure.
  13. Disney, Donald Ray; Darwish, Mohamed, High-voltage lateral transistor with a multi-layered extended drain structure.
  14. Disney, Donald Ray; Paul, Amit, High-voltage lateral transistor with a multi-layered extended drain structure.
  15. Disney,Donald Ray; Paul,Amit, High-voltage lateral transistor with a multi-layered extended drain structure.
  16. Disney, Donald Ray, High-voltage transistor with JFET conduction channels.
  17. Disney, Donald Ray, High-voltage transistor with buried conduction layer.
  18. Disney, Donald Ray, High-voltage transistor with buried conduction layer.
  19. Donald Ray Disney, High-voltage transistor with buried conduction layer.
  20. Donald Ray Disney, High-voltage transistor with buried conduction layer.
  21. Donald Ray Disney, High-voltage transistor with buried conduction layer.
  22. Rumennik Vladimir ; Disney Donald R. ; Ajit Janardhanan S., High-voltage transistor with multi-layer conduction region.
  23. Rumennik, Valdimir; Disney, Donald R.; Ajit, Janardhanan S., High-voltage transistor with multi-layer conduction region.
  24. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., High-voltage transistor with multi-layer conduction region.
  25. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., High-voltage transistor with multi-layer conduction region.
  26. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., High-voltage transistor with multi-layer conduction region.
  27. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., High-voltage transistor with multi-layer conduction region.
  28. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., High-voltage transistor with multi-layer conduction region.
  29. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., High-voltage transistor with multi-layer conduction region.
  30. Banerjee,Sujit; Disney,Donald Ray, High-voltage vertical transistor with a multi-gradient drain doping profile.
  31. Banerjee,Sujit; Disney,Donald Ray, High-voltage vertical transistor with a multi-gradient drain doping profile.
  32. Banerjee,Sujit; Disney,Donald Ray, High-voltage vertical transistor with a multi-gradient drain doping profile.
  33. Disney, Donald Ray, High-voltage vertical transistor with a multi-layered extended drain structure.
  34. Disney, Donald Ray, High-voltage vertical transistor with a multi-layered extended drain structure.
  35. Disney, Donald Ray, High-voltage vertical transistor with a multi-layered extended drain structure.
  36. Disney, Donald Ray, High-voltage vertical transistor with a multi-layered extended drain structure.
  37. Siu Stephen N., Insert-molded leadframe to optimize interface between powertrain and driver board.
  38. Disney, Donald Ray, Integrated circuit with closely coupled high voltage output and offline transistor pair.
  39. Disney, Donald Ray, Integrated circuit with closely coupled high voltage output and offline transistor pair.
  40. Balakrishnan,Balu, Integrated circuit with multi-length output transistor segment.
  41. Balakrishnan, Balu, Integrated circuit with multi-length output transistor segments.
  42. Balakrishnan,Balu, Integrated circuit with multi-length output transistor segments.
  43. Disney, Donald Ray; Grabowski, Wayne Bryan, Lateral power MOSFET for high switching speeds.
  44. Disney, Donald Ray; Grabowski, Wayne Bryan, Lateral power MOSFET for high switching speeds.
  45. Disney,Donald Ray; Grabowski,Wayne Bryan, Lateral power MOSFET for high switching speeds.
  46. Disney Donald R. ; Djenguerian Alex B., Lateral power MOSFET with improved gate design.
  47. Keller Richard A. (Palo Alto CA), Linear load circuit to control switching power supplies under minimum load conditions.
  48. Keller Richard A. (Palo Alto CA), Low noise voltage regulator and method using a gated single ended oscillator.
  49. Rumennik Vladimir (Los Altos CA), MOS gated bipolar transistor.
  50. Yang Thomas (Hsin-Chu TWX), Method for manufacturing a hybrid circuit charge-coupled device image sensor.
  51. Fujii Hiroyuki (Osaka JPX) Tateno Kenichi (Shiga JPX) Nishikawa Mikio (Kyoto JPX), Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor.
  52. Disney, Donald Ray, Method of fabricating a high-voltage transistor.
  53. Disney, Donald Ray, Method of fabricating a high-voltage transistor.
  54. Donald Ray Disney, Method of fabricating a high-voltage transistor.
  55. Donald Ray Disney, Method of fabricating a high-voltage transistor.
  56. Disney, Donald Ray, Method of fabricating a high-voltage transistor with a multi-layered extended drain structure.
  57. Disney, Donald Ray, Method of fabricating a high-voltage transistor with a multi-layered extended drain structure.
  58. Disney, Donald Ray, Method of fabricating a high-voltage transistor with a multi-layered extended drain structure.
  59. Disney, Donald Ray, Method of fabricating a high-voltage transistor with a multi-layered extended drain structure.
  60. Disney,Donald Ray, Method of fabricating a high-voltage transistor with an extended drain structure.
  61. Disney, Donald Ray, Method of fabricating complementary high-voltage field-effect transistors.
  62. Disney, Donald Ray, Method of fabricating high-voltage transistor with buried conduction layer.
  63. Balakrishnan,Balu, Method of forming an integrated circuit with multi-length power transistor segments.
  64. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., Method of making a high-voltage transistor with buried conduction regions.
  65. Rumennik, Vladimir; Disney, Donald R.; Ajit, Janardhanan S., Method of making a high-voltage transistor with buried conduction regions.
  66. Rumennik Vladimir ; Disney Donald R. ; Ajit Janardhanan S., Method of making a high-voltage transistor with multiple lateral conduction layers.
  67. Grabowski Wayne B. (Mountain View CA) Rumennik Vladimir (Los Altos CA), Method of making high voltage transistor.
  68. Balakrishnan,Balu, Method of manufacturing an integrated circuit with multilength power transistor elements.
  69. Rumennik Vladimir (Los Altos CA) Busse Robert W. (Mountain View CA), Narrow radius tips for high voltage semiconductor devices with interdigitated source and drain electrodes.
  70. Balakrishnan, Balu; Hawthorne, Brad L.; Bäurle, Stefan, Package for a power semiconductor device.
  71. Yasui Mitsuru (Yokohama JPX), Plastic enclosing device.
  72. Disney, Donald Ray, Power integrated circuit with distributed gate driver.
  73. Disney, Donald Ray, Power integrated circuit with distributed gate driver.
  74. Leman Brooks R. (Santa Clara CA), Regulated flyback converter with spike suppressing coupled inductors.
  75. Parthasarathy, Vijay; Grabowski, Wayne Bryan, Segmented pillar layout for a high-voltage vertical transistor.
  76. Sawaya Hiromichi (Kawasaki JPX), Semiconductor device.
  77. Hayashi,Kenichi; Kawafuji,Hisashi; Murai,Junichi; Izuta,Goro, Semiconductor device and semiconductor assembly module with a gap-controlling lead structure.
  78. Majumdar Gourab (Tokyo JPX) Mori Satoshi (Tokyo JPX) Noda Sukehisa (Tokyo JPX) Iwagami Tooru (Tokyo JPX) Takagi Yoshio (Tokyo JPX) Kawafuji Hisashi (Tokyo JPX), Semiconductor device and semiconductor module.
  79. Mangiagli Marcantonio,ITX ; Pogliese Rosario,ITX, Semiconductor device having alternating electrically insulative coated leads.
  80. Son,Joon seo; Nam,Shi baek; Jeon,O seob, Semiconductor package suitable for high voltage applications.
  81. Yoshida, Hiroshi; Kawafuji, Hisashi, Semiconductor unit.
  82. Sato Mitsutaka (Kawasaki JPX) Yoshimoto Masanori (Kawasaki JPX), Single in-line package for surface mounting.

이 특허를 인용한 특허 (1)

  1. Lu, Kai; Zhao, Zhenqing; Hong, Shouyu; Wang, Tao; Liang, Le, Package module of power conversion circuit and manufacturing method thereof.
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