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Performing a deterministic reduction operation in a parallel computer that includes compute nodes, each of which includes computer processors and a CAU (Collectives Acceleration Unit) that couples computer processors to one another for data communications, including organizing processors and a CAU i

Performing a deterministic reduction operation in a parallel computer that includes compute nodes, each of which includes computer processors and a CAU (Collectives Acceleration Unit) that couples computer processors to one another for data communications, including organizing processors and a CAU into a branched tree topology in which the CAU is a root and the processors are children; receiving, from each of the processors in any order, dummy contribution data, where each processor is restricted from sending any other data to the root CAU prior to receiving an acknowledgement of receipt from the root CAU; sending, by the root CAU to the processors in the branched tree topology, in a predefined order, acknowledgements of receipt of the dummy contribution data; receiving, by the root CAU from the processors in the predefined order, the processors' contribution data to the reduction operation; and reducing, by the root CAU, the processors' contribution data.

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1. An apparatus for performing a deterministic reduction operation in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node comprising a plurality of computer processors and a Collectives Acceleration Unit (CAU), the CAU coupling computer processors of

1. An apparatus for performing a deterministic reduction operation in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node comprising a plurality of computer processors and a Collectives Acceleration Unit (CAU), the CAU coupling computer processors of compute nodes to one another for data communications in a cluster data communications network, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory including computer program instructions that, when executed by the computer processor, carry out the steps of: organizing a first plurality of processors of the parallel computer and a first CAU into a branched tree topology, wherein the first CAU comprises a root of the branched tree topology and the first plurality of processors comprise children of the root CAU;receiving, by the root CAU from each of the processors in the branched tree topology, in any order, dummy contribution data, wherein each processor in the branched tree topology is restricted from sending any other data to the root CAU prior to receiving an acknowledgement of receipt from the root CAU;sending, by the root CAU to the processors in the branched tree topology, in a predefined order, acknowledgements of receipt of the dummy contribution data;providing, by each processor in the branched tree topology, the processor's contribution data to the root CAU only after receiving an acknowledgement;receiving, by the root CAU from the processors in the branched tree topology in the predefined order, the first plurality of processors' contribution data to the reduction operation; andreducing, by the root CAU, the contribution data of the processors in the branched tree topology. 2. The apparatus of claim 1 wherein sending acknowledgements of receipt of the dummy contribution data, providing the processor's contribution data, receiving the contribution data, and reducing the first plurality of processors' contribution data is carried out iteratively, in pairs of processors, in the predefined order. 3. The apparatus of claim 1 wherein sending acknowledgements of receipt of the dummy contribution data further comprises sending acknowledgements only after receiving dummy contribution data from all processors in the branched tree topology. 4. The apparatus of claim 3 wherein: receiving dummy contribution data further comprises incrementing a counter upon receipt of dummy contribution data from each processor in the branched tree topology; andsending acknowledgements only after receiving dummy contribution data from all processors in the branched tree topology further comprises sending acknowledgements only after the counter equals the number of processors in the branched tree topology. 5. The apparatus of claim 1 wherein each processor comprises an 8-core central processing unit (CPU), each compute node comprises four processors, and the four processors of each compute node comprise a 32-way symmetric multiprocessing system (SMP). 6. The apparatus of claim 1 wherein each CAU further comprises an arithmetic logic unit (ALU) and is configured to accelerate collective operations processing by performing one or more arithmetic operations without use of a processor of a compute node. 7. A computer program product for performing a deterministic reduction operation in a parallel computer, the parallel computer comprising a plurality of compute nodes, each compute node comprising a plurality of computer processors and a Collectives Acceleration Unit (CAU), the CAU coupling computer processors of compute nodes to one another for data communications in a cluster data communications network, the computer program product disposed upon a computer readable storage medium wherein the computer readable storage medium is not a signal, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of: organizing a first plurality of processors of the parallel computer and a first CAU into a branched tree topology, wherein the first CAU comprises a root of the branched tree topology and the first plurality of processors comprise children of the root CAU;receiving, by the root CAU from each of the processors in the branched tree topology, in any order, dummy contribution data, wherein each processor in the branched tree topology is restricted from sending any other data to the root CAU prior to receiving an acknowledgement of receipt from the root CAU;sending, by the root CAU to the processors in the branched tree topology, in a predefined order, acknowledgements of receipt of the dummy contribution data;providing, by each processor in the branched tree topology, the processor's contribution data to the root CAU only after receiving an acknowledgement;receiving, by the root CAU from the processors in the branched tree topology in the predefined order, the first plurality of processors' contribution data to the reduction operation; andreducing, by the root CAU, the contribution data of the processors in the branched tree topology. 8. The computer program product of claim 7 wherein sending acknowledgements of receipt of the dummy contribution data, providing the processor's contribution data, receiving the contribution data, and reducing the first plurality of processors' contribution data is carried out iteratively, in pairs of processors, in the predefined order. 9. The computer program product of claim 7 wherein sending acknowledgements of receipt of the dummy contribution data further comprises sending acknowledgements only after receiving dummy contribution data from all processors in the branched tree topology. 10. The computer program product of claim 9 wherein: receiving dummy contribution data further comprises incrementing a counter upon receipt of dummy contribution data from each processor in the branched tree topology; andsending acknowledgements only after receiving dummy contribution data from all processors in the branched tree topology further comprises sending acknowledgements only after the counter equals the number of processors in the branched tree topology. 11. The computer program product of claim 7 wherein each processor comprises an 8-core central processing unit (CPU), each compute node comprises four processors, and the four processors of each compute node comprise a 32-way symmetric multiprocessing system (SMP). 12. The computer program product of claim 7 wherein each CAU further comprises an arithmetic logic unit (ALU) and is configured to accelerate collective operations processing by performing one or more arithmetic operations without use of a processor of a compute node.